tile: BaseTile refactor, pt 1
* Make dts generation reusable across tile subclasses * First attempt to standardize tile IO nodes and connect methods * hartid => hartId when talking about scala Ints
This commit is contained in:
Henry Cook
@ -22,7 +22,7 @@ case class RocketTileParams(
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trace: Boolean = false,
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hcfOnUncorrectable: Boolean = false,
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name: Option[String] = Some("tile"),
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hartid: Int = 0,
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hartId: Int = 0,
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blockerCtrlAddr: Option[BigInt] = None,
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boundaryBuffers: Boolean = false // if synthesized with hierarchical PnR, cut feed-throughs?
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) extends TileParams {
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@ -30,117 +30,32 @@ case class RocketTileParams(
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require(dcache.isDefined)
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}
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abstract class HartedTile(tileParams: TileParams, val hartid: Int)(implicit p: Parameters) extends BaseTile(tileParams)(p) {
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require (log2Up(hartid + 1) <= p(MaxHartIdBits), s"p(MaxHartIdBits) of ${p(MaxHartIdBits)} is not enough for hartid ${hartid}")
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}
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class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) extends HartedTile(rocketParams, rocketParams.hartid)(p)
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class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) extends BaseTile(rocketParams)(p)
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with HasExternalInterrupts
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with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
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with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend
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nDCachePorts += 1 // core TODO dcachePorts += () => module.core.io.dmem ??
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private def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
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private def ofStr(x: String) = Seq(ResourceString(x))
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private def ofRef(x: Device) = Seq(ResourceReference(x.label))
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val dtimProperty = scratch.map(d => Map(
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"sifive,dtim" -> d.device.asProperty)).getOrElse(Nil)
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val itimProperty = tileParams.icache.flatMap(_.itimAddr.map(i => Map(
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"sifive,itim" -> frontend.icache.device.asProperty))).getOrElse(Nil)
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val cpuDevice = new Device {
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def describe(resources: ResourceBindings): Description = {
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val block = p(CacheBlockBytes)
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val m = if (rocketParams.core.mulDiv.nonEmpty) "m" else ""
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val a = if (rocketParams.core.useAtomics) "a" else ""
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val f = if (rocketParams.core.fpu.nonEmpty) "f" else ""
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val d = if (rocketParams.core.fpu.nonEmpty && p(XLen) > 32) "d" else ""
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val c = if (rocketParams.core.useCompressed) "c" else ""
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val isa = s"rv${p(XLen)}i$m$a$f$d$c"
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val dcache = rocketParams.dcache.filter(!_.scratch.isDefined).map(d => Map(
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"d-cache-block-size" -> ofInt(block),
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"d-cache-sets" -> ofInt(d.nSets),
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"d-cache-size" -> ofInt(d.nSets * d.nWays * block))).getOrElse(Map())
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val dtim = scratch.map(d => Map(
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"sifive,dtim" -> ofRef(d.device))).getOrElse(Map())
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val itim = if (frontend.icache.slaveNode.edges.in.isEmpty) Map() else Map(
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"sifive,itim" -> ofRef(frontend.icache.device))
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val incoherent = if (!rocketParams.core.useAtomicsOnlyForIO) Map() else Map(
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"sifive,d-cache-incoherent" -> Nil)
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val icache = rocketParams.icache.map(i => Map(
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"i-cache-block-size" -> ofInt(block),
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"i-cache-sets" -> ofInt(i.nSets),
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"i-cache-size" -> ofInt(i.nSets * i.nWays * block))).getOrElse(Map())
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val dtlb = rocketParams.dcache.filter(_ => rocketParams.core.useVM).map(d => Map(
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"d-tlb-size" -> ofInt(d.nTLBEntries),
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"d-tlb-sets" -> ofInt(1))).getOrElse(Map())
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val itlb = rocketParams.icache.filter(_ => rocketParams.core.useVM).map(i => Map(
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"i-tlb-size" -> ofInt(i.nTLBEntries),
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"i-tlb-sets" -> ofInt(1))).getOrElse(Map())
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val mmu = if (!rocketParams.core.useVM) Map() else Map(
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"tlb-split" -> Nil,
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"mmu-type" -> ofStr(p(PgLevels) match {
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case 2 => "riscv,sv32"
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case 3 => "riscv,sv39"
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case 4 => "riscv,sv48"
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}))
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// Find all the caches
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val outer = masterNode.edges.out
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.flatMap(_.manager.managers)
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.filter(_.supportsAcquireB)
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.flatMap(_.resources.headOption)
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.map(_.owner.label)
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.distinct
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val nextlevel: Option[(String, Seq[ResourceValue])] =
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if (outer.isEmpty) None else
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Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList)
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Description(s"cpus/cpu@${hartid}", Map(
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"reg" -> resources("reg").map(_.value),
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"device_type" -> ofStr("cpu"),
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"compatible" -> Seq(ResourceString("sifive,rocket0"), ResourceString("riscv")),
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"status" -> ofStr("okay"),
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"clock-frequency" -> Seq(ResourceInt(rocketParams.core.bootFreqHz)),
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"riscv,isa" -> ofStr(isa),
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"timebase-frequency" -> Seq(ResourceInt(p(DTSTimebase)))) ++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb ++ dtim ++ itim ++ incoherent)
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}
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}
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val intcDevice = new Device {
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def describe(resources: ResourceBindings): Description = {
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Description(s"cpus/cpu@${hartid}/interrupt-controller", Map(
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"compatible" -> ofStr("riscv,cpu-intc"),
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"interrupt-controller" -> Nil,
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"#interrupt-cells" -> ofInt(1)))
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}
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def describe(resources: ResourceBindings): Description =
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toDescription(resources)("sifive,rocket0", dtimProperty ++ itimProperty)
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}
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ResourceBinding {
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Resource(cpuDevice, "reg").bind(ResourceInt(BigInt(hartid)))
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Resource(intcDevice, "reg").bind(ResourceInt(BigInt(hartid)))
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intNode.edges.in.flatMap(_.source.sources).map { case s =>
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for (i <- s.range.start until s.range.end) {
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csrIntMap.lift(i).foreach { j =>
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s.resources.foreach { r =>
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r.bind(intcDevice, ResourceInt(j))
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}
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}
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}
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}
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Resource(cpuDevice, "reg").bind(ResourceInt(BigInt(hartId)))
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}
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override lazy val module = new RocketTileModule(this)
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}
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class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
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with HasExternalInterruptsBundle
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with CanHaveScratchpadBundle
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with CanHaltAndCatchFire {
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val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(Bool(OUTPUT))
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}
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@ -203,7 +118,7 @@ class RocketTileWrapper(
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// The buffers needed to cut feed-through paths are microarchitecture specific, so belong here
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val masterBuffer = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)))
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val masterNode: TLOutwardNode = crossing match {
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val masterNode = crossing match {
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case _: AsynchronousCrossing => rocket.masterNode
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case SynchronousCrossing(b) =>
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require (!params.boundaryBuffers || (b.depth >= 1 && !b.flow && !b.pipe), "Buffer misconfiguration creates feed-through paths")
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@ -229,9 +144,9 @@ class RocketTileWrapper(
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}
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}
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val intXbar = LazyModule(new IntXbar)
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val localIntNode = Some(intXbar.intnode)
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rocket.intNode := intXbar.intnode
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rocket.intInwardNode := intXbar.intnode
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val intInwardNode = intXbar.intnode
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val intOutwardNode = rocket.intOutwardNode
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override lazy val module = new BaseTileModule(this, () => new RocketTileWrapperBundle(this)) {
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// signals that do not change based on crossing type:
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