riscv/rocket-chip
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tile: BaseTile refactor, pt 1

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* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
This commit is contained in:
Henry Cook
2017-12-20 17:18:38 -08:00
parent ba6dd160a3
commit 1cd018546c
18 changed files with 210 additions and 189 deletions
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31
src/main/scala/tile/Interrupts.scala
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@ -5,6 +5,7 @@ package freechips.rocketchip.tile
import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
@ -22,8 +23,30 @@ trait HasExternalInterrupts extends HasTileParameters {
implicit val p: Parameters
val module: HasExternalInterruptsModule
val intNode = IntSinkNode(IntSinkPortSimple())
val localIntNode: Option[IntInwardNode] = None
val intInwardNode = IntSinkNode(IntSinkPortSimple())
val intcDevice = new Device {
def describe(resources: ResourceBindings): Description = {
Description(s"cpus/cpu@$hartId/interrupt-controller", Map(
"compatible" -> "riscv,cpu-intc".asProperty,
"interrupt-controller" -> Nil,
"#interrupt-cells" -> 1.asProperty))
}
}
ResourceBinding {
Resource(intcDevice, "reg").bind(ResourceInt(BigInt(hartId)))
intInwardNode.edges.in.flatMap(_.source.sources).map { case s =>
for (i <- s.range.start until s.range.end) {
csrIntMap.lift(i).foreach { j =>
s.resources.foreach { r =>
r.bind(intcDevice, ResourceInt(j))
}
}
}
}
}
// TODO: the order of the following two functions must match, and
// also match the order which things are connected to the
@ -35,6 +58,7 @@ trait HasExternalInterrupts extends HasTileParameters {
val seip = if (usingVM) Seq(9) else Nil
List(65535, 3, 7, 11) ++ seip ++ List.tabulate(nlips)(_ + 16)
}
}
trait HasExternalInterruptsBundle {
@ -43,7 +67,6 @@ trait HasExternalInterruptsBundle {
trait HasExternalInterruptsModule {
val outer: HasExternalInterrupts
val io: HasExternalInterruptsBundle
// go from flat diplomatic Interrupts to bundled TileInterrupts
def decodeCoreInterrupts(core: TileInterrupts) {
@ -57,7 +80,7 @@ trait HasExternalInterruptsModule {
val core_ips = core.lip
val (interrupts, _) = outer.intNode.in(0)
val (interrupts, _) = outer.intInwardNode.in(0)
(async_ips ++ periph_ips ++ seip ++ core_ips).zip(interrupts).foreach { case(c, i) => c := i }
}
}