tile: BaseTile refactor, pt 1

* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints

src/main/scala/tile/BaseTile.scala

@@ -5,6 +5,7 @@ package freechips.rocketchip.tile
 import Chisel._
 
 import freechips.rocketchip.config._
+import freechips.rocketchip.coreplex.{CacheBlockBytes, SystemBusKey}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.rocket._
@@ -23,7 +24,7 @@ trait TileParams {
   val rocc: Seq[RoCCParams]
   val btb: Option[BTBParams]
   val trace: Boolean
-  val hartid: Int
+  val hartId: Int
   val blockerCtrlAddr: Option[BigInt]
 }
 
@@ -63,10 +64,61 @@ trait HasTileParameters {
   def vaddrBitsExtended: Int = vpnBitsExtended + pgIdxBits
   def maxPAddrBits: Int = xLen match { case 32 => 34; case 64 => 56 }
 
+  def hartId: Int = tileParams.hartId
   def hartIdLen: Int = p(MaxHartIdBits)
   def resetVectorLen: Int = paddrBits
 
+  def cacheBlockBytes = p(CacheBlockBytes)
+  def lgCacheBlockBytes = log2Up(cacheBlockBytes)
+  def masterPortBeatBytes = p(SystemBusKey).beatBytes
+
   def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size
+
+  // TODO merge with isaString in CSR.scala
+  def isaDTS: String = {
+    val m = if (tileParams.core.mulDiv.nonEmpty) "m" else ""
+    val a = if (tileParams.core.useAtomics) "a" else ""
+    val f = if (tileParams.core.fpu.nonEmpty) "f" else ""
+    val d = if (tileParams.core.fpu.nonEmpty && p(XLen) > 32) "d" else ""
+    val c = if (tileParams.core.useCompressed) "c" else ""
+    s"rv${p(XLen)}i$m$a$f$d$c"
+  }
+
+  def tileProperties: PropertyMap = {
+    val dcache = tileParams.dcache.filter(!_.scratch.isDefined).map(d => Map(
+      "d-cache-block-size"   -> cacheBlockBytes.asProperty,
+      "d-cache-sets"         -> d.nSets.asProperty,
+      "d-cache-size"         -> (d.nSets * d.nWays * cacheBlockBytes).asProperty)
+    ).getOrElse(Nil)
+
+    val incoherent = if (!tileParams.core.useAtomicsOnlyForIO) Nil else Map(
+      "sifive,d-cache-incoherent" -> Nil)
+
+    val icache = tileParams.icache.map(i => Map(
+      "i-cache-block-size"   -> cacheBlockBytes.asProperty,
+      "i-cache-sets"         -> i.nSets.asProperty,
+      "i-cache-size"         -> (i.nSets * i.nWays * cacheBlockBytes).asProperty)
+    ).getOrElse(Nil)
+
+    val dtlb = tileParams.dcache.filter(_ => tileParams.core.useVM).map(d => Map(
+      "d-tlb-size"           -> d.nTLBEntries.asProperty,
+      "d-tlb-sets"           -> 1.asProperty)).getOrElse(Nil)
+
+    val itlb = tileParams.icache.filter(_ => tileParams.core.useVM).map(i => Map(
+      "i-tlb-size"           -> i.nTLBEntries.asProperty,
+      "i-tlb-sets"           -> 1.asProperty)).getOrElse(Nil)
+
+    val mmu = if (!tileParams.core.useVM) Nil else Map(
+        "tlb-split" -> Nil,
+        "mmu-type"  -> (p(PgLevels) match {
+          case 2 => "riscv,sv32"
+          case 3 => "riscv,sv39"
+          case 4 => "riscv,sv48"
+        }).asProperty)
+
+    dcache ++ icache ++ dtlb ++ itlb ++ mmu ++ incoherent
+  }
+
 }
 
 abstract class BareTile(implicit p: Parameters) extends LazyModule
@@ -81,23 +133,6 @@ abstract class BareTileModule[+L <: BareTile, +B <: BareTileBundle[L]](_outer: L
   val io = IO(_io ())
 }
 
-/** Uses TileLink master port to connect caches and accelerators to the coreplex */
-trait HasTileLinkMasterPort {
-  implicit val p: Parameters
-  val module: HasTileLinkMasterPortModule
-  val masterNode = TLIdentityNode()
-  val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to
-}
-
-trait HasTileLinkMasterPortBundle {
-  val outer: HasTileLinkMasterPort
-}
-
-trait HasTileLinkMasterPortModule {
-  val outer: HasTileLinkMasterPort
-  val io: HasTileLinkMasterPortBundle
-}
-
 /** Some other standard inputs */
 trait HasExternallyDrivenTileConstants extends Bundle with HasTileParameters {
   val hartid = UInt(INPUT, hartIdLen)
@@ -112,7 +147,48 @@ trait CanHaveInstructionTracePort extends Bundle with HasTileParameters {
 abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends BareTile
     with HasTileParameters {
   def module: BaseTileModule[BaseTile, BaseTileBundle[BaseTile]]
-  val localIntNode: Option[IntInwardNode]
+  def masterNode: TLOutwardNode
+  def slaveNode: TLInwardNode
+  def intInwardNode: IntInwardNode
+  def intOutwardNode: IntOutwardNode
+
+  protected val tlOtherMastersNode = TLIdentityNode()
+  protected val tlMasterXbar = LazyModule(new TLXbar)
+  protected val tlSlaveXbar = LazyModule(new TLXbar)
+  protected val intXbar = LazyModule(new IntXbar)
+
+  def connectTLSlave(node: TLNode, bytes: Int) {
+    DisableMonitors { implicit p =>
+      (Seq(node, TLFragmenter(bytes, cacheBlockBytes, earlyAck=EarlyAck.PutFulls))
+        ++ (xBytes != bytes).option(TLWidthWidget(xBytes)))
+        .foldRight(tlSlaveXbar.node:TLOutwardNode)(_ :*= _)
+    }
+  }
+
+  // Find resource labels for all the outward caches
+  def nextLevelCacheProperty: PropertyOption = {
+    val outer = tlMasterXbar.node.edges.out
+      .flatMap(_.manager.managers)
+      .filter(_.supportsAcquireB)
+      .flatMap(_.resources.headOption)
+      .map(_.owner.label)
+      .distinct
+    if (outer.isEmpty) None
+    else Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList)
+  }
+
+  def toDescription(resources: ResourceBindings)(compat: String, extraProperties: PropertyMap = Nil): Description = {
+    val cpuProperties: PropertyMap = Map(
+        "reg"                  -> resources("reg").map(_.value),
+        "device_type"          -> "cpu".asProperty,
+        "compatible"           -> Seq(ResourceString(compat), ResourceString("riscv")),
+        "status"               -> "okay".asProperty,
+        "clock-frequency"      -> tileParams.core.bootFreqHz.asProperty,
+        "riscv,isa"            -> isaDTS.asProperty,
+        "timebase-frequency"   -> p(DTSTimebase).asProperty)
+
+    Description(s"cpus/cpu@${hartId}", (cpuProperties ++ nextLevelCacheProperty ++ tileProperties ++ extraProperties).toMap)
+  }
 }
 
 abstract class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
@@ -126,4 +202,5 @@ class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: ()
   require(paddrBits <= maxPAddrBits)
   require(resetVectorLen <= xLen)
   require(resetVectorLen <= vaddrBitsExtended)
+  require (log2Up(hartId + 1) <= hartIdLen, s"p(MaxHartIdBits) of $hartIdLen is not enough for hartid $hartId")
 }