tile: BaseTile refactor, pt 1

* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints

src/main/scala/tile/BaseTile.scala

@@ -5,6 +5,7 @@ package freechips.rocketchip.tile
 import Chisel._
 
 import freechips.rocketchip.config._
+import freechips.rocketchip.coreplex.{CacheBlockBytes, SystemBusKey}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.rocket._
@@ -23,7 +24,7 @@ trait TileParams {
   val rocc: Seq[RoCCParams]
   val btb: Option[BTBParams]
   val trace: Boolean
-  val hartid: Int
+  val hartId: Int
   val blockerCtrlAddr: Option[BigInt]
 }
 
@@ -63,10 +64,61 @@ trait HasTileParameters {
   def vaddrBitsExtended: Int = vpnBitsExtended + pgIdxBits
   def maxPAddrBits: Int = xLen match { case 32 => 34; case 64 => 56 }
 
+  def hartId: Int = tileParams.hartId
   def hartIdLen: Int = p(MaxHartIdBits)
   def resetVectorLen: Int = paddrBits
 
+  def cacheBlockBytes = p(CacheBlockBytes)
+  def lgCacheBlockBytes = log2Up(cacheBlockBytes)
+  def masterPortBeatBytes = p(SystemBusKey).beatBytes
+
   def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size
+
+  // TODO merge with isaString in CSR.scala
+  def isaDTS: String = {
+    val m = if (tileParams.core.mulDiv.nonEmpty) "m" else ""
+    val a = if (tileParams.core.useAtomics) "a" else ""
+    val f = if (tileParams.core.fpu.nonEmpty) "f" else ""
+    val d = if (tileParams.core.fpu.nonEmpty && p(XLen) > 32) "d" else ""
+    val c = if (tileParams.core.useCompressed) "c" else ""
+    s"rv${p(XLen)}i$m$a$f$d$c"
+  }
+
+  def tileProperties: PropertyMap = {
+    val dcache = tileParams.dcache.filter(!_.scratch.isDefined).map(d => Map(
+      "d-cache-block-size"   -> cacheBlockBytes.asProperty,
+      "d-cache-sets"         -> d.nSets.asProperty,
+      "d-cache-size"         -> (d.nSets * d.nWays * cacheBlockBytes).asProperty)
+    ).getOrElse(Nil)
+
+    val incoherent = if (!tileParams.core.useAtomicsOnlyForIO) Nil else Map(
+      "sifive,d-cache-incoherent" -> Nil)
+
+    val icache = tileParams.icache.map(i => Map(
+      "i-cache-block-size"   -> cacheBlockBytes.asProperty,
+      "i-cache-sets"         -> i.nSets.asProperty,
+      "i-cache-size"         -> (i.nSets * i.nWays * cacheBlockBytes).asProperty)
+    ).getOrElse(Nil)
+
+    val dtlb = tileParams.dcache.filter(_ => tileParams.core.useVM).map(d => Map(
+      "d-tlb-size"           -> d.nTLBEntries.asProperty,
+      "d-tlb-sets"           -> 1.asProperty)).getOrElse(Nil)
+
+    val itlb = tileParams.icache.filter(_ => tileParams.core.useVM).map(i => Map(
+      "i-tlb-size"           -> i.nTLBEntries.asProperty,
+      "i-tlb-sets"           -> 1.asProperty)).getOrElse(Nil)
+
+    val mmu = if (!tileParams.core.useVM) Nil else Map(
+        "tlb-split" -> Nil,
+        "mmu-type"  -> (p(PgLevels) match {
+          case 2 => "riscv,sv32"
+          case 3 => "riscv,sv39"
+          case 4 => "riscv,sv48"
+        }).asProperty)
+
+    dcache ++ icache ++ dtlb ++ itlb ++ mmu ++ incoherent
+  }
+
 }
 
 abstract class BareTile(implicit p: Parameters) extends LazyModule
@@ -81,23 +133,6 @@ abstract class BareTileModule[+L <: BareTile, +B <: BareTileBundle[L]](_outer: L
   val io = IO(_io ())
 }
 
-/** Uses TileLink master port to connect caches and accelerators to the coreplex */
-trait HasTileLinkMasterPort {
-  implicit val p: Parameters
-  val module: HasTileLinkMasterPortModule
-  val masterNode = TLIdentityNode()
-  val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to
-}
-
-trait HasTileLinkMasterPortBundle {
-  val outer: HasTileLinkMasterPort
-}
-
-trait HasTileLinkMasterPortModule {
-  val outer: HasTileLinkMasterPort
-  val io: HasTileLinkMasterPortBundle
-}
-
 /** Some other standard inputs */
 trait HasExternallyDrivenTileConstants extends Bundle with HasTileParameters {
   val hartid = UInt(INPUT, hartIdLen)
@@ -112,7 +147,48 @@ trait CanHaveInstructionTracePort extends Bundle with HasTileParameters {
 abstract class BaseTile(tileParams: TileParams)(implicit p: Parameters) extends BareTile
     with HasTileParameters {
   def module: BaseTileModule[BaseTile, BaseTileBundle[BaseTile]]
-  val localIntNode: Option[IntInwardNode]
+  def masterNode: TLOutwardNode
+  def slaveNode: TLInwardNode
+  def intInwardNode: IntInwardNode
+  def intOutwardNode: IntOutwardNode
+
+  protected val tlOtherMastersNode = TLIdentityNode()
+  protected val tlMasterXbar = LazyModule(new TLXbar)
+  protected val tlSlaveXbar = LazyModule(new TLXbar)
+  protected val intXbar = LazyModule(new IntXbar)
+
+  def connectTLSlave(node: TLNode, bytes: Int) {
+    DisableMonitors { implicit p =>
+      (Seq(node, TLFragmenter(bytes, cacheBlockBytes, earlyAck=EarlyAck.PutFulls))
+        ++ (xBytes != bytes).option(TLWidthWidget(xBytes)))
+        .foldRight(tlSlaveXbar.node:TLOutwardNode)(_ :*= _)
+    }
+  }
+
+  // Find resource labels for all the outward caches
+  def nextLevelCacheProperty: PropertyOption = {
+    val outer = tlMasterXbar.node.edges.out
+      .flatMap(_.manager.managers)
+      .filter(_.supportsAcquireB)
+      .flatMap(_.resources.headOption)
+      .map(_.owner.label)
+      .distinct
+    if (outer.isEmpty) None
+    else Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList)
+  }
+
+  def toDescription(resources: ResourceBindings)(compat: String, extraProperties: PropertyMap = Nil): Description = {
+    val cpuProperties: PropertyMap = Map(
+        "reg"                  -> resources("reg").map(_.value),
+        "device_type"          -> "cpu".asProperty,
+        "compatible"           -> Seq(ResourceString(compat), ResourceString("riscv")),
+        "status"               -> "okay".asProperty,
+        "clock-frequency"      -> tileParams.core.bootFreqHz.asProperty,
+        "riscv,isa"            -> isaDTS.asProperty,
+        "timebase-frequency"   -> p(DTSTimebase).asProperty)
+
+    Description(s"cpus/cpu@${hartId}", (cpuProperties ++ nextLevelCacheProperty ++ tileProperties ++ extraProperties).toMap)
+  }
 }
 
 abstract class BaseTileBundle[+L <: BaseTile](_outer: L) extends BareTileBundle(_outer)
@@ -126,4 +202,5 @@ class BaseTileModule[+L <: BaseTile, +B <: BaseTileBundle[L]](_outer: L, _io: ()
   require(paddrBits <= maxPAddrBits)
   require(resetVectorLen <= xLen)
   require(resetVectorLen <= vaddrBitsExtended)
+  require (log2Up(hartId + 1) <= hartIdLen, s"p(MaxHartIdBits) of $hartIdLen is not enough for hartid $hartId")
 }

src/main/scala/tile/Core.scala

@@ -13,6 +13,7 @@ case object XLen extends Field[Int]
 
 // These parameters can be varied per-core
 trait CoreParams {
+  val bootFreqHz: BigInt
   val useVM: Boolean
   val useUser: Boolean
   val useDebug: Boolean

src/main/scala/tile/Interrupts.scala

@@ -5,6 +5,7 @@ package freechips.rocketchip.tile
 import Chisel._
 
 import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.util._
 
@@ -22,8 +23,30 @@ trait HasExternalInterrupts extends HasTileParameters {
   implicit val p: Parameters
   val module: HasExternalInterruptsModule
 
-  val intNode = IntSinkNode(IntSinkPortSimple())
-  val localIntNode: Option[IntInwardNode] = None
+  val intInwardNode = IntSinkNode(IntSinkPortSimple())
+
+  val intcDevice = new Device {
+    def describe(resources: ResourceBindings): Description = {
+      Description(s"cpus/cpu@$hartId/interrupt-controller", Map(
+        "compatible"           -> "riscv,cpu-intc".asProperty,
+        "interrupt-controller" -> Nil,
+        "#interrupt-cells"     -> 1.asProperty))
+    }
+  }
+
+  ResourceBinding {
+    Resource(intcDevice, "reg").bind(ResourceInt(BigInt(hartId)))
+
+    intInwardNode.edges.in.flatMap(_.source.sources).map { case s =>
+      for (i <- s.range.start until s.range.end) {
+       csrIntMap.lift(i).foreach { j =>
+          s.resources.foreach { r =>
+            r.bind(intcDevice, ResourceInt(j))
+          }
+        }
+      }
+    }
+  }
 
   // TODO: the order of the following two functions must match, and
   //         also match the order which things are connected to the
@@ -35,6 +58,7 @@ trait HasExternalInterrupts extends HasTileParameters {
     val seip = if (usingVM) Seq(9) else Nil
     List(65535, 3, 7, 11) ++ seip ++ List.tabulate(nlips)(_ + 16)
   }
+
 }
 
 trait HasExternalInterruptsBundle {
@@ -43,7 +67,6 @@ trait HasExternalInterruptsBundle {
 
 trait HasExternalInterruptsModule {
   val outer: HasExternalInterrupts
-  val io: HasExternalInterruptsBundle
 
   // go from flat diplomatic Interrupts to bundled TileInterrupts
   def decodeCoreInterrupts(core: TileInterrupts) {
@@ -57,7 +80,7 @@ trait HasExternalInterruptsModule {
 
     val core_ips = core.lip
 
-    val (interrupts, _) = outer.intNode.in(0)
+    val (interrupts, _) = outer.intInwardNode.in(0)
     (async_ips ++ periph_ips ++ seip ++ core_ips).zip(interrupts).foreach { case(c, i) => c := i }
   }
 }

src/main/scala/tile/L1Cache.scala

@@ -14,16 +14,13 @@ trait L1CacheParams {
   def nWays:         Int
   def rowBits:       Int
   def nTLBEntries:   Int
-  def blockBytes:    Int
+  def blockBytes:    Int // TODO this is ignored in favor of p(CacheBlockBytes) in BaseTile
 }
 
-trait HasL1CacheParameters {
-  implicit val p: Parameters
+trait HasL1CacheParameters extends HasTileParameters {
   val cacheParams: L1CacheParams
   private val bundleParams = p(SharedMemoryTLEdge).bundle
 
-  def cacheBlockBytes = cacheParams.blockBytes
-  def lgCacheBlockBytes = log2Up(cacheBlockBytes)
   def nSets = cacheParams.nSets
   def blockOffBits = lgCacheBlockBytes
   def idxBits = log2Up(cacheParams.nSets)

src/main/scala/tile/LazyRoCC.scala

@@ -77,7 +77,7 @@ class LazyRoCCModule(outer: LazyRoCC) extends LazyModuleImp(outer) {
 
 /** Mixins for including RoCC **/
 
-trait HasLazyRoCC extends CanHaveSharedFPU with CanHavePTW with HasTileLinkMasterPort {
+trait HasLazyRoCC extends CanHaveSharedFPU with CanHavePTW { this: BaseTile =>
   implicit val p: Parameters
   val module: HasLazyRoCCModule
 
@@ -86,8 +86,8 @@ trait HasLazyRoCC extends CanHaveSharedFPU with CanHavePTW with HasTileLinkMaste
       case RoccNPTWPorts => accelParams.nPTWPorts
   }))}
 
-  roccs.map(_.atlNode).foreach { atl => tileBus.node :=* atl }
-  roccs.map(_.tlNode).foreach { tl => masterNode :=* tl }
+  roccs.map(_.atlNode).foreach { atl => tlMasterXbar.node :=* atl }
+  roccs.map(_.tlNode).foreach { tl => tlOtherMastersNode :=* tl }
 
   nPTWPorts += p(BuildRoCC).map(_.nPTWPorts).foldLeft(0)(_ + _)
   nDCachePorts += roccs.size
@@ -95,8 +95,7 @@ trait HasLazyRoCC extends CanHaveSharedFPU with CanHavePTW with HasTileLinkMaste
 
 trait HasLazyRoCCModule extends CanHaveSharedFPUModule
   with CanHavePTWModule
-  with HasCoreParameters
-  with HasTileLinkMasterPortModule {
+  with HasCoreParameters {
   val outer: HasLazyRoCC
   val roccCore = Wire(new RoCCCoreIO()(outer.p))
 

src/main/scala/tile/RocketTile.scala

@@ -22,7 +22,7 @@ case class RocketTileParams(
     trace: Boolean = false,
     hcfOnUncorrectable: Boolean = false,
     name: Option[String] = Some("tile"),
-    hartid: Int = 0,
+    hartId: Int = 0,
     blockerCtrlAddr: Option[BigInt] = None,
     boundaryBuffers: Boolean = false // if synthesized with hierarchical PnR, cut feed-throughs?
     ) extends TileParams {
@@ -30,117 +30,32 @@ case class RocketTileParams(
   require(dcache.isDefined)
 }
 
-abstract class HartedTile(tileParams: TileParams, val hartid: Int)(implicit p: Parameters) extends BaseTile(tileParams)(p) {
-  require (log2Up(hartid + 1) <= p(MaxHartIdBits), s"p(MaxHartIdBits) of ${p(MaxHartIdBits)} is not enough for hartid ${hartid}")
-}
-
-class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) extends HartedTile(rocketParams, rocketParams.hartid)(p)
+class RocketTile(val rocketParams: RocketTileParams)(implicit p: Parameters) extends BaseTile(rocketParams)(p)
     with HasExternalInterrupts
     with HasLazyRoCC  // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache
     with CanHaveScratchpad { // implies CanHavePTW with HasHellaCache with HasICacheFrontend
 
   nDCachePorts += 1 // core TODO dcachePorts += () => module.core.io.dmem ??
 
-  private def ofInt(x: Int) = Seq(ResourceInt(BigInt(x)))
-  private def ofStr(x: String) = Seq(ResourceString(x))
-  private def ofRef(x: Device) = Seq(ResourceReference(x.label))
+  val dtimProperty = scratch.map(d => Map(
+    "sifive,dtim" -> d.device.asProperty)).getOrElse(Nil)
+
+  val itimProperty = tileParams.icache.flatMap(_.itimAddr.map(i => Map(
+    "sifive,itim" -> frontend.icache.device.asProperty))).getOrElse(Nil)
 
   val cpuDevice = new Device {
-    def describe(resources: ResourceBindings): Description = {
-      val block =  p(CacheBlockBytes)
-      val m = if (rocketParams.core.mulDiv.nonEmpty) "m" else ""
-      val a = if (rocketParams.core.useAtomics) "a" else ""
-      val f = if (rocketParams.core.fpu.nonEmpty) "f" else ""
-      val d = if (rocketParams.core.fpu.nonEmpty && p(XLen) > 32) "d" else ""
-      val c = if (rocketParams.core.useCompressed) "c" else ""
-      val isa = s"rv${p(XLen)}i$m$a$f$d$c"
-
-      val dcache = rocketParams.dcache.filter(!_.scratch.isDefined).map(d => Map(
-        "d-cache-block-size"   -> ofInt(block),
-        "d-cache-sets"         -> ofInt(d.nSets),
-        "d-cache-size"         -> ofInt(d.nSets * d.nWays * block))).getOrElse(Map())
-
-      val dtim = scratch.map(d => Map(
-        "sifive,dtim"          -> ofRef(d.device))).getOrElse(Map())
-
-      val itim = if (frontend.icache.slaveNode.edges.in.isEmpty) Map() else Map(
-        "sifive,itim"          -> ofRef(frontend.icache.device))
-
-      val incoherent = if (!rocketParams.core.useAtomicsOnlyForIO) Map() else Map(
-        "sifive,d-cache-incoherent" -> Nil)
-
-      val icache = rocketParams.icache.map(i => Map(
-        "i-cache-block-size"   -> ofInt(block),
-        "i-cache-sets"         -> ofInt(i.nSets),
-        "i-cache-size"         -> ofInt(i.nSets * i.nWays * block))).getOrElse(Map())
-
-      val dtlb = rocketParams.dcache.filter(_ => rocketParams.core.useVM).map(d => Map(
-        "d-tlb-size"           -> ofInt(d.nTLBEntries),
-        "d-tlb-sets"           -> ofInt(1))).getOrElse(Map())
-
-      val itlb = rocketParams.icache.filter(_ => rocketParams.core.useVM).map(i => Map(
-        "i-tlb-size"           -> ofInt(i.nTLBEntries),
-        "i-tlb-sets"           -> ofInt(1))).getOrElse(Map())
-
-      val mmu = if (!rocketParams.core.useVM) Map() else Map(
-        "tlb-split" -> Nil,
-        "mmu-type"  -> ofStr(p(PgLevels) match {
-          case 2 => "riscv,sv32"
-          case 3 => "riscv,sv39"
-          case 4 => "riscv,sv48"
-      }))
-
-      // Find all the caches
-      val outer = masterNode.edges.out
-        .flatMap(_.manager.managers)
-        .filter(_.supportsAcquireB)
-        .flatMap(_.resources.headOption)
-        .map(_.owner.label)
-        .distinct
-      val nextlevel: Option[(String, Seq[ResourceValue])] =
-        if (outer.isEmpty) None else
-        Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList)
-
-      Description(s"cpus/cpu@${hartid}", Map(
-        "reg"                  -> resources("reg").map(_.value),
-        "device_type"          -> ofStr("cpu"),
-        "compatible"           -> Seq(ResourceString("sifive,rocket0"), ResourceString("riscv")),
-        "status"               -> ofStr("okay"),
-        "clock-frequency"      -> Seq(ResourceInt(rocketParams.core.bootFreqHz)),
-        "riscv,isa"            -> ofStr(isa),
-        "timebase-frequency"   -> Seq(ResourceInt(p(DTSTimebase)))) ++ dcache ++ icache ++ nextlevel ++ mmu ++ itlb ++ dtlb ++ dtim ++ itim ++ incoherent)
-    }
-  }
-  val intcDevice = new Device {
-    def describe(resources: ResourceBindings): Description = {
-      Description(s"cpus/cpu@${hartid}/interrupt-controller", Map(
-        "compatible"           -> ofStr("riscv,cpu-intc"),
-        "interrupt-controller" -> Nil,
-        "#interrupt-cells"     -> ofInt(1)))
-    }
+    def describe(resources: ResourceBindings): Description =
+      toDescription(resources)("sifive,rocket0", dtimProperty ++ itimProperty)
   }
 
   ResourceBinding {
-    Resource(cpuDevice, "reg").bind(ResourceInt(BigInt(hartid)))
-    Resource(intcDevice, "reg").bind(ResourceInt(BigInt(hartid)))
-
-    intNode.edges.in.flatMap(_.source.sources).map { case s =>
-      for (i <- s.range.start until s.range.end) {
-       csrIntMap.lift(i).foreach { j =>
-          s.resources.foreach { r =>
-            r.bind(intcDevice, ResourceInt(j))
-          }
-        }
-      }
-    }
+    Resource(cpuDevice, "reg").bind(ResourceInt(BigInt(hartId)))
   }
 
   override lazy val module = new RocketTileModule(this)
 }
 
 class RocketTileBundle(outer: RocketTile) extends BaseTileBundle(outer)
-    with HasExternalInterruptsBundle
-    with CanHaveScratchpadBundle
     with CanHaltAndCatchFire {
   val halt_and_catch_fire = outer.rocketParams.hcfOnUncorrectable.option(Bool(OUTPUT))
 }
@@ -203,7 +118,7 @@ class RocketTileWrapper(
 
   // The buffers needed to cut feed-through paths are microarchitecture specific, so belong here
   val masterBuffer = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)))
-  val masterNode: TLOutwardNode = crossing match {
+  val masterNode = crossing match {
     case _: AsynchronousCrossing => rocket.masterNode
     case SynchronousCrossing(b) =>
       require (!params.boundaryBuffers || (b.depth >= 1 && !b.flow && !b.pipe), "Buffer misconfiguration creates feed-through paths")
@@ -229,9 +144,9 @@ class RocketTileWrapper(
       }
   }
 
-  val intXbar = LazyModule(new IntXbar)
-  val localIntNode = Some(intXbar.intnode)
-  rocket.intNode := intXbar.intnode
+  rocket.intInwardNode := intXbar.intnode
+  val intInwardNode = intXbar.intnode
+  val intOutwardNode = rocket.intOutwardNode
 
   override lazy val module = new BaseTileModule(this, () => new RocketTileWrapperBundle(this)) {
     // signals that do not change based on crossing type: