riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tile: BaseTile refactor, pt 1

Browse Source 
* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
This commit is contained in:
Henry Cook
2017-12-20 17:18:38 -08:00
parent ba6dd160a3
commit 1cd018546c
18 changed files with 210 additions and 189 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
src/main/scala/rocket/Frontend.scala
View File

@ -307,19 +307,19 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
}
/** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
trait HasICacheFrontend extends CanHavePTW { this: BaseTile =>
val module: HasICacheFrontendModule
val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int))
val hartid: Int
tileBus.node := frontend.masterNode
val frontend = LazyModule(new Frontend(tileParams.icache.get, hartId))
tlMasterXbar.node := frontend.masterNode
connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes)
nPTWPorts += 1
}
trait HasICacheFrontendBundle extends HasTileLinkMasterPortBundle {
trait HasICacheFrontendBundle {
val outer: HasICacheFrontend
}
trait HasICacheFrontendModule extends CanHavePTWModule with HasTileLinkMasterPortModule {
trait HasICacheFrontendModule extends CanHavePTWModule {
val outer: HasICacheFrontend
ptwPorts += outer.frontend.module.io.ptw
}