tile: BaseTile refactor, pt 1

* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints

src/main/scala/rocket/Frontend.scala

@@ -307,19 +307,19 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
 }
 
 /** Mix-ins for constructing tiles that have an ICache-based pipeline frontend */
-trait HasICacheFrontend extends CanHavePTW with HasTileLinkMasterPort {
+trait HasICacheFrontend extends CanHavePTW { this: BaseTile =>
   val module: HasICacheFrontendModule
-  val frontend = LazyModule(new Frontend(tileParams.icache.get, hartid: Int))
-  val hartid: Int
-  tileBus.node := frontend.masterNode
+  val frontend = LazyModule(new Frontend(tileParams.icache.get, hartId))
+  tlMasterXbar.node := frontend.masterNode
+  connectTLSlave(frontend.slaveNode, tileParams.core.fetchBytes)
   nPTWPorts += 1
 }
 
-trait HasICacheFrontendBundle extends HasTileLinkMasterPortBundle {
+trait HasICacheFrontendBundle {
   val outer: HasICacheFrontend
 }
 
-trait HasICacheFrontendModule extends CanHavePTWModule with HasTileLinkMasterPortModule {
+trait HasICacheFrontendModule extends CanHavePTWModule {
   val outer: HasICacheFrontend
   ptwPorts += outer.frontend.module.io.ptw
 }

src/main/scala/rocket/HellaCache.scala

@@ -194,25 +194,24 @@ class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
 
 /** Mix-ins for constructing tiles that have a HellaCache */
 
-trait HasHellaCache extends HasTileLinkMasterPort with HasTileParameters {
+trait HasHellaCache extends HasTileParameters { this: BaseTile =>
   val module: HasHellaCacheModule
   implicit val p: Parameters
   def findScratchpadFromICache: Option[AddressSet]
-  val hartid: Int
   var nDCachePorts = 0
   val dcache: HellaCache = LazyModule(
     if(tileParams.dcache.get.nMSHRs == 0) {
-      new DCache(hartid, findScratchpadFromICache _, p(RocketCrossingKey).head.knownRatio)
-    } else { new NonBlockingDCache(hartid) })
+      new DCache(hartId, findScratchpadFromICache _, p(RocketCrossingKey).head.knownRatio)
+    } else { new NonBlockingDCache(hartId) })
 
-  tileBus.node := dcache.node
+  tlMasterXbar.node := dcache.node
 }
 
-trait HasHellaCacheBundle extends HasTileLinkMasterPortBundle {
+trait HasHellaCacheBundle {
   val outer: HasHellaCache
 }
 
-trait HasHellaCacheModule extends HasTileLinkMasterPortModule {
+trait HasHellaCacheModule {
   val outer: HasHellaCache
   //val io: HasHellaCacheBundle
   val dcachePorts = ListBuffer[HellaCacheIO]()

src/main/scala/rocket/ICache.scala

@@ -45,11 +45,11 @@ class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p)
   val uncorrectable = (cacheParams.itimAddr.nonEmpty && cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
 }
 
-class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parameters) extends LazyModule {
+class ICache(val icacheParams: ICacheParams, val hartId: Int)(implicit p: Parameters) extends LazyModule {
   lazy val module = new ICacheModule(this)
   val masterNode = TLClientNode(Seq(TLClientPortParameters(Seq(TLClientParameters(
     sourceId = IdRange(0, 1 + icacheParams.prefetch.toInt), // 0=refill, 1=hint
-    name = s"Core ${hartid} ICache")))))
+    name = s"Core ${hartId} ICache")))))
 
   val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
   val device = new SimpleDevice("itim", Seq("sifive,itim0"))
@@ -100,7 +100,7 @@ class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
 // get a tile-specific property without breaking deduplication
 object GetPropertyByHartId {
   def apply[T <: Data](tiles: Seq[RocketTileParams], f: RocketTileParams => Option[T], hartId: UInt): T = {
-    PriorityMux(tiles.collect { case t if f(t).isDefined => (t.hartid === hartId) -> f(t).get })
+    PriorityMux(tiles.collect { case t if f(t).isDefined => (t.hartId === hartId) -> f(t).get })
   }
 }
 

src/main/scala/rocket/PTW.scala

@@ -287,7 +287,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
 }
 
 /** Mix-ins for constructing tiles that might have a PTW */
-trait CanHavePTW extends HasHellaCache {
+trait CanHavePTW extends HasHellaCache { this: BaseTile =>
   implicit val p: Parameters
   val module: CanHavePTWModule
   var nPTWPorts = 1

src/main/scala/rocket/ScratchpadSlavePort.scala

@@ -6,7 +6,6 @@ import Chisel._
 import Chisel.ImplicitConversions._
 
 import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.coreplex.{CacheBlockBytes, SystemBusKey}
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tile._
@@ -96,19 +95,22 @@ class ScratchpadSlavePort(address: AddressSet, coreDataBytes: Int, usingAtomics:
 }
 
 /** Mix-ins for constructing tiles that have optional scratchpads */
-trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
+trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend { this: BaseTile =>
   val module: CanHaveScratchpadModule
-  val cacheBlockBytes = p(CacheBlockBytes)
-  val masterPortBeatBytes = p(SystemBusKey).beatBytes
+
+  val intOutwardNode = IntIdentityNode()
+  val slaveNode = TLIdentityNode()
+  val masterNode = TLIdentityNode()
 
   val scratch = tileParams.dcache.flatMap { d => d.scratch.map(s =>
     LazyModule(new ScratchpadSlavePort(AddressSet(s, d.dataScratchpadBytes-1), xBytes, tileParams.core.useAtomics && !tileParams.core.useAtomicsOnlyForIO)))
   }
+  scratch.foreach(lm => connectTLSlave(lm.node, xBytes))
 
-  val intOutputNode = tileParams.core.tileControlAddr.map(dummy => IntIdentityNode())
   val busErrorUnit = tileParams.core.tileControlAddr map { a =>
     val beu = LazyModule(new BusErrorUnit(new L1BusErrors, BusErrorUnitParams(a)))
-    intOutputNode.get := beu.intNode
+    intOutwardNode := beu.intNode
+    connectTLSlave(beu.node, xBytes)
     beu
   }
 
@@ -117,27 +119,13 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
       .map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true))
       .map(bp => LazyModule(new BasicBusBlocker(bp)))
 
-  masterNode := tile_master_blocker.map { _.node := tileBus.node } getOrElse { tileBus.node }
+  tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes))
 
-  // connect any combination of ITIM, DTIM, and BusErrorUnit
-  val slaveNode = TLIdentityNode()
-  DisableMonitors { implicit p =>
-    val xbarPorts =
-      scratch.map(lm => (lm.node, xBytes)) ++
-      busErrorUnit.map(lm => (lm.node, xBytes)) ++
-      tileParams.icache.flatMap(icache => icache.itimAddr.map(a => (frontend.slaveNode, tileParams.core.fetchBytes))) ++
-      tile_master_blocker.map( lm => (lm.controlNode, xBytes))
+  // TODO: this doesn't block other masters, e.g. RoCCs
+  tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node }
+  masterNode :=* tlOtherMastersNode
+  tlSlaveXbar.node :*= slaveNode 
 
-    if (xbarPorts.nonEmpty) {
-      val xbar = LazyModule(new TLXbar)
-      xbar.node := slaveNode
-      xbarPorts.foreach { case (port, bytes) =>
-        (Seq(port, TLFragmenter(bytes, cacheBlockBytes, earlyAck=EarlyAck.PutFulls))
-          ++ (xBytes != bytes).option(TLWidthWidget(xBytes)))
-          .foldRight(xbar.node:TLOutwardNode)(_ := _)
-      }
-    }
-  }
 
   def findScratchpadFromICache: Option[AddressSet] = scratch.map { s =>
     val finalNode = frontend.masterNode.edges.out.head.manager.managers.find(_.nodePath.last == s.node)
@@ -155,7 +143,6 @@ trait CanHaveScratchpadBundle extends HasHellaCacheBundle with HasICacheFrontend
 
 trait CanHaveScratchpadModule extends HasHellaCacheModule with HasICacheFrontendModule {
   val outer: CanHaveScratchpad
-  val io: CanHaveScratchpadBundle
 
   outer.scratch.foreach { lm => dcachePorts += lm.module.io.dmem }
   outer.busErrorUnit.foreach { lm =>