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tile: BaseTile refactor, pt 1

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* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
This commit is contained in:
Henry Cook
2017-12-20 17:18:38 -08:00
parent ba6dd160a3
commit 1cd018546c
18 changed files with 210 additions and 189 deletions
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4
src/main/scala/groundtest/TraceGen.scala
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@ -23,6 +23,7 @@ import Chisel._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.rocket._
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import scala.util.Random
@ -65,7 +66,7 @@ case class TraceGenParams(
memStart: BigInt, //p(ExtMem).base
numGens: Int) extends GroundTestTileParams {
def build(i: Int, p: Parameters): GroundTestTile = new TraceGenTile(i, this)(p)
val hartid = 0
val hartId = 0
val trace = false
val blockerCtrlAddr = None
}
@ -578,6 +579,7 @@ class TraceGenerator(val params: TraceGenParams)(implicit val p: Parameters) ext
// =======================
class TraceGenTile(val id: Int, val params: TraceGenParams)(implicit p: Parameters) extends GroundTestTile(params) {
val masterNode: TLOutwardNode = dcacheOpt.map(_.node).getOrElse(TLIdentityNode())
override lazy val module = new TraceGenTileModule(this)
}