tile: BaseTile refactor, pt 1

* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints

src/main/scala/groundtest/Tile.scala

@@ -7,8 +7,10 @@ import Chisel._
 import freechips.rocketchip.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.coreplex._
+import freechips.rocketchip.interrupts._
 import freechips.rocketchip.rocket.{DCache, RocketCoreParams}
 import freechips.rocketchip.tile._
+import freechips.rocketchip.tilelink._
 import scala.collection.mutable.ListBuffer
 
 trait GroundTestTileParams extends TileParams {
@@ -29,8 +31,10 @@ trait GroundTestTileParams extends TileParams {
 case object GroundTestTilesKey extends Field[Seq[GroundTestTileParams]]
 
 abstract class GroundTestTile(params: GroundTestTileParams)(implicit p: Parameters) extends BaseTile(params)(p) {
-  val slave = None
-  val localIntNode = None
+  val intInwardNode: IntInwardNode = IntIdentityNode()
+  val intOutwardNode: IntOutwardNode = IntIdentityNode()
+  val slaveNode: TLInwardNode = TLIdentityNode()
+
   val dcacheOpt = params.dcache.map { dc => LazyModule(new DCache(0)) }
 
   override lazy val module = new GroundTestTileModule(this, () => new GroundTestTileBundle(this))

src/main/scala/groundtest/TraceGen.scala

@@ -23,6 +23,7 @@ import Chisel._
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.tile._
+import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 import scala.util.Random
 
@@ -65,7 +66,7 @@ case class TraceGenParams(
     memStart: BigInt, //p(ExtMem).base
     numGens: Int) extends GroundTestTileParams {
   def build(i: Int, p: Parameters): GroundTestTile = new TraceGenTile(i, this)(p)
-  val hartid = 0
+  val hartId = 0
   val trace = false
   val blockerCtrlAddr = None
 }
@@ -578,6 +579,7 @@ class TraceGenerator(val params: TraceGenParams)(implicit val p: Parameters) ext
 // =======================
 
 class TraceGenTile(val id: Int, val params: TraceGenParams)(implicit p: Parameters) extends GroundTestTile(params) {
+  val masterNode: TLOutwardNode = dcacheOpt.map(_.node).getOrElse(TLIdentityNode())
   override lazy val module = new TraceGenTileModule(this)
 }