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tile: BaseTile refactor, pt 1

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* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
This commit is contained in:
Henry Cook
2017-12-20 17:18:38 -08:00
parent ba6dd160a3
commit 1cd018546c
18 changed files with 210 additions and 189 deletions
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4
src/main/scala/coreplex/Configs.scala
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@ -45,7 +45,7 @@ class WithNBigCores(n: Int) extends Config((site, here, up) => {
icache = Some(ICacheParams(
rowBits = site(SystemBusKey).beatBits,
blockBytes = site(CacheBlockBytes))))
List.tabulate(n)(i => big.copy(hartid = i))
List.tabulate(n)(i => big.copy(hartId = i))
}
})
@ -67,7 +67,7 @@ class WithNSmallCores(n: Int) extends Config((site, here, up) => {
nWays = 1,
nTLBEntries = 4,
blockBytes = site(CacheBlockBytes))))
List.tabulate(n)(i => small.copy(hartid = i))
List.tabulate(n)(i => small.copy(hartId = i))
}
})

2
src/main/scala/coreplex/HasTiles.scala
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@ -17,7 +17,7 @@ trait HasTiles extends HasSystemBus {
val tiles: Seq[BaseTile]
protected def tileParams: Seq[TileParams] = tiles.map(_.tileParams)
def nTiles: Int = tileParams.size
def hartIdList: Seq[Int] = tileParams.map(_.hartid)
def hartIdList: Seq[Int] = tileParams.map(_.hartId)
def localIntCounts: Seq[Int] = tileParams.map(_.core.nLocalInterrupts)
}

12
src/main/scala/coreplex/RocketCoreplex.scala
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@ -110,22 +110,20 @@ trait HasRocketTiles extends HasTiles
// are decoded from rocket.intNode inside the tile.
// 1. always async crossing for debug
wrapper.intXbar.intnode := wrapper { IntSyncCrossingSink(3) } := debug.intnode
wrapper.intInwardNode := wrapper { IntSyncCrossingSink(3) } := debug.intnode
// 2. clint+plic conditionally crossing
val periphIntNode = wrapper.intXbar.intnode :=* wrapper.crossIntIn
val periphIntNode = wrapper.intInwardNode :=* wrapper.crossIntIn
periphIntNode := clint.intnode // msip+mtip
periphIntNode := plic.intnode // meip
if (tp.core.useVM) periphIntNode := plic.intnode // seip
// 3. local interrupts never cross
// this.localIntNode is wired up externally // lip
// this.intInwardNode is wired up externally // lip
// 4. conditional crossing from core to PLIC
wrapper.rocket.intOutputNode.foreach { i =>
FlipRendering { implicit p =>
plic.intnode :=* wrapper.crossIntOut :=* i
}
FlipRendering { implicit p =>
plic.intnode :=* wrapper.crossIntOut :=* wrapper.intOutwardNode
}
wrapper