riscv/rocket-chip
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Merge pull request #1003 from freechipsproject/ma-fetch

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Don't write badaddr on misaligned fetch exceptions
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Henry Cook 2017-09-20 14:28:26 -07:00 committed by GitHub
commit 1cb91eed41
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/CSR.scala
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@ -520,7 +520,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param
val epc = ~(~io.pc | (coreInstBytes-1)) val epc = ~(~io.pc | (coreInstBytes-1))
val write_badaddr = cause isOneOf (Causes.illegal_instruction, Causes.breakpoint, val write_badaddr = cause isOneOf (Causes.illegal_instruction, Causes.breakpoint,
Causes.misaligned_load, Causes.misaligned_store, Causes.misaligned_fetch, Causes.misaligned_load, Causes.misaligned_store,
Causes.load_access, Causes.store_access, Causes.fetch_access, Causes.load_access, Causes.store_access, Causes.fetch_access,
Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault) Causes.load_page_fault, Causes.store_page_fault, Causes.fetch_page_fault)
val badaddr_value = Mux(write_badaddr, io.badaddr, 0.U) val badaddr_value = Mux(write_badaddr, io.badaddr, 0.U)