riscv/rocket-chip
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allow re-positionable PLIC and Clint, and change coreplex internal network names

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This commit is contained in:
Henry Cook
2017-06-20 16:11:57 -07:00
parent 5552f23294
commit 1c97a2a94c
12 changed files with 65 additions and 58 deletions
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16
src/main/scala/uncore/devices/Clint.scala
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@ -14,9 +14,6 @@ import scala.math.{min,max}
import config._
import tile.XLen
/** Number of tiles */
case object NTiles extends Field[Int]
object ClintConsts
{
def msipOffset(hart: Int) = hart * msipBytes
@ -30,7 +27,12 @@ object ClintConsts
def ints = 2
}
class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Parameters) extends LazyModule
case class ClintParams(baseAddress: BigInt = 0x02000000)
{
def address = AddressSet(baseAddress, ClintConsts.size-1)
}
class CoreplexLocalInterrupter(nTiles: Int, params: ClintParams)(implicit p: Parameters) extends LazyModule
{
import ClintConsts._
@ -40,7 +42,7 @@ class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Paramet
}
val node = TLRegisterNode(
address = Seq(AddressSet(address, size-1)),
address = Seq(params.address),
device = device,
beatBytes = p(XLen)/8)
@ -64,8 +66,8 @@ class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Paramet
reg := newTime >> i
}
val timecmp = Seq.fill(p(NTiles)) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) }
val ipi = Seq.fill(p(NTiles)) { RegInit(UInt(0, width = 1)) }
val timecmp = Seq.fill(nTiles) { Seq.fill(timeWidth/regWidth)(Reg(UInt(width = regWidth))) }
val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) }
io.int.zipWithIndex.foreach { case (int, i) =>
int(0) := ipi(i)(0) // msip

12
src/main/scala/uncore/devices/Plic.scala
View File

@ -53,11 +53,15 @@ object PLICConsts
require(hartBase >= enableBase(maxHarts))
}
/** Platform-Level Interrupt Controller */
class TLPLIC(maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parameters) extends LazyModule
case class PLICParams(baseAddress: BigInt = 0xC000000, maxPriorities: Int = 7)
{
require (maxPriorities >= 0)
def address = AddressSet(baseAddress, PLICConsts.size-1)
}
/** Platform-Level Interrupt Controller */
class TLPLIC(params: PLICParams)(implicit p: Parameters) extends LazyModule
{
// plic0 => max devices 1023
val device = new SimpleDevice("interrupt-controller", Seq("riscv,plic0")) {
override val alwaysExtended = true
@ -73,7 +77,7 @@ class TLPLIC(maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parame
}
val node = TLRegisterNode(
address = Seq(AddressSet(address, PLICConsts.size-1)),
address = Seq(params.address),
device = device,
beatBytes = p(XLen)/8,
undefZero = false,
@ -87,7 +91,7 @@ class TLPLIC(maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parame
/* Negotiated sizes */
def nDevices: Int = intnode.edgesIn.map(_.source.num).sum
def nPriorities = min(maxPriorities, nDevices)
def nPriorities = min(params.maxPriorities, nDevices)
def nHarts = intnode.edgesOut.map(_.source.num).sum
// Assign all the devices unique ranges