riscv/rocket-chip
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allow re-positionable PLIC and Clint, and change coreplex internal network names

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This commit is contained in:
Henry Cook
2017-06-20 16:11:57 -07:00
parent 5552f23294
commit 1c97a2a94c
12 changed files with 65 additions and 58 deletions
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4
src/main/scala/groundtest/Coreplex.scala
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@ -44,8 +44,8 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
tile_splitter.node :=* fixer.node
tiles.foreach { fixer.node :=* _.masterNode }
val cbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, cbus_beatBytes))
cbusRAM.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbusBlockBytes))
pbusRAM.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node)
override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))
}