allow re-positionable PLIC and Clint, and change coreplex internal network names

src/main/scala/groundtest/Configs.scala

@@ -10,7 +10,6 @@ import uncore.tilelink._
 import uncore.coherence._
 import uncore.agents._
 import uncore.util._
-import uncore.devices.NTiles
 import tile.TileKey
 import junctions._
 import config._

src/main/scala/groundtest/Coreplex.scala

@@ -44,8 +44,8 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
   tile_splitter.node :=* fixer.node
   tiles.foreach { fixer.node :=* _.masterNode }
 
-  val cbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, cbus_beatBytes))
-  cbusRAM.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
+  val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, pbusBlockBytes))
+  pbusRAM.node := TLFragmenter(pbusBeatBytes, pbusBlockBytes)(pbus.node)
 
   override lazy val module = new GroundTestCoreplexModule(this, () => new GroundTestCoreplexBundle(this))
 }

src/main/scala/groundtest/TraceGen.scala

@@ -22,7 +22,7 @@ package groundtest
 import Chisel._
 import uncore.tilelink._
 import uncore.constants._
-import uncore.devices.NTiles
+import coreplex.NTiles
 import rocket._
 import tile._
 import util.{Timer, DynamicTimer}

src/main/scala/groundtest/TrafficGenerator.scala

@@ -5,7 +5,7 @@ package groundtest
 
 import Chisel._
 import uncore.tilelink._
-import uncore.devices.NTiles
+import coreplex.NTiles
 import uncore.constants._
 import junctions._
 import rocket._