riscv/rocket-chip
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allow re-positionable PLIC and Clint, and change coreplex internal network names

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This commit is contained in:
Henry Cook
2017-06-20 16:11:57 -07:00
parent 5552f23294
commit 1c97a2a94c
12 changed files with 65 additions and 58 deletions
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src/main/scala/coreplex/Configs.scala
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@@ -21,11 +21,12 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
case XLen => 64 // Applies to all cores
case ResetVectorBits => site(PAddrBits)
case MaxHartIdBits => log2Up(site(NTiles))
case MaxPriorityLevels => 7
case BuildCore => (p: Parameters) => new Rocket()(p)
case RocketCrossing => SynchronousCrossing()
case RocketTilesKey => Nil
case DMKey => DefaultDebugModuleConfig(site(XLen))
case PLICKey => PLICParams()
case ClintKey => ClintParams()
case NTiles => site(RocketTilesKey).size
case CBusConfig => TLBusConfig(beatBytes = site(XLen)/8)
case L1toL2Config => TLBusConfig(beatBytes = site(XLen)/8) // increase for more PCIe bandwidth