riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

axi4 Fragmenter: initialize error response to 0

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-10-13 13:46:24 -07:00
parent 958af132ba
commit 1c79a23a8b
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/uncore/axi4/Fragmenter.scala
View File

@ -225,7 +225,7 @@ class AXI4Fragmenter(lite: Boolean = false, maxInFlight: Int = 32, combinational
in_b.bits := out_b.bits in_b.bits := out_b.bits
// Merge errors from dropped B responses // Merge errors from dropped B responses
val r_resp = Reg(UInt(width = AXI4Parameters.respBits)) val r_resp = RegInit(UInt(0, width = AXI4Parameters.respBits))
val resp = out_b.bits.resp | r_resp val resp = out_b.bits.resp | r_resp
when (out_b.fire()) { r_resp := Mux(b_last, UInt(0), resp) } when (out_b.fire()) { r_resp := Mux(b_last, UInt(0), resp) }
in_b.bits.resp := resp in_b.bits.resp := resp