Merge pull request #918 from freechipsproject/icache-prefetch
Icache prefetch
This commit is contained in:
Andrew Waterman
GitHub
commit
1be1433f04
@ -141,6 +141,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
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icache.io.s2_vaddr := s2_pc
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icache.io.s1_kill := s2_redirect || tlb.io.resp.miss || s2_replay
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icache.io.s2_kill := s2_speculative && !s2_tlb_resp.cacheable || s2_xcpt
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icache.io.s2_prefetch := s2_tlb_resp.prefetchable
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fq.io.enq.valid := s2_valid && (icache.io.resp.valid || !s2_tlb_resp.miss && icache.io.s2_kill)
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fq.io.enq.bits.pc := s2_pc
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@ -21,6 +21,7 @@ case class ICacheParams(
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tagECC: Code = new IdentityCode,
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dataECC: Code = new IdentityCode,
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itimAddr: Option[BigInt] = None,
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prefetch: Boolean = false,
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blockBytes: Int = 64,
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latency: Int = 2,
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fetchBytes: Int = 4) extends L1CacheParams {
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@ -37,7 +38,9 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
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class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parameters) extends LazyModule {
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lazy val module = new ICacheModule(this)
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val masterNode = TLClientNode(TLClientParameters(name = s"Core ${hartid} ICache"))
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val masterNode = TLClientNode(TLClientParameters(
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sourceId = IdRange(0, 1 + icacheParams.prefetch.toInt), // 0=refill, 1=hint
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name = s"Core ${hartid} ICache"))
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val size = icacheParams.nSets * icacheParams.nWays * icacheParams.blockBytes
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val device = new SimpleDevice("itim", Seq("sifive,itim0"))
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@ -72,6 +75,7 @@ class ICacheBundle(outer: ICache) extends CoreBundle()(outer.p) {
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val s2_vaddr = UInt(INPUT, vaddrBits) // delayed two cycles w.r.t. req
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val s1_kill = Bool(INPUT) // delayed one cycle w.r.t. req
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val s2_kill = Bool(INPUT) // delayed two cycles; prevents I$ miss emission
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val s2_prefetch = Bool(INPUT) // should I$ prefetch next line on a miss?
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val resp = Valid(new ICacheResp(outer))
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val invalidate = Bool(INPUT)
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@ -126,23 +130,28 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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val invalidated = Reg(Bool())
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val refill_valid = RegInit(false.B)
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val send_hint = RegInit(false.B)
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val refill_fire = tl_out.a.fire() && !send_hint
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val hint_outstanding = RegInit(false.B)
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val s2_miss = s2_valid && !s2_hit && !io.s2_kill && !RegNext(refill_valid)
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val refill_addr = RegEnable(io.s1_paddr, s1_valid && !(refill_valid || s2_miss))
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val refill_tag = refill_addr(tagBits+untagBits-1,untagBits)
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val refill_idx = refill_addr(untagBits-1,blockOffBits)
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val refill_one_beat = tl_out.d.fire() && edge_out.hasData(tl_out.d.bits)
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io.req.ready := !(tl_out.d.fire() || s0_slaveValid || s3_slaveValid)
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io.req.ready := !(refill_one_beat || s0_slaveValid || s3_slaveValid)
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val s0_valid = io.req.fire()
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val s0_vaddr = io.req.bits.addr
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s1_valid := s0_valid
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val (_, _, refill_done, refill_cnt) = edge_out.count(tl_out.d)
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val (_, _, d_done, refill_cnt) = edge_out.count(tl_out.d)
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val refill_done = refill_one_beat && d_done
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tl_out.d.ready := !s3_slaveValid
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require (edge_out.manager.minLatency > 0)
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val repl_way = if (isDM) UInt(0) else {
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// pick a way that is not used by the scratchpad
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val v0 = LFSR16(tl_out.a.fire())(log2Up(nWays)-1,0)
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val v0 = LFSR16(refill_fire)(log2Up(nWays)-1,0)
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var v = v0
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for (i <- log2Ceil(nWays) - 1 to 0 by -1) {
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val mask = nWays - (BigInt(1) << (i + 1))
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@ -162,7 +171,7 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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}
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val vb_array = Reg(init=Bits(0, nSets*nWays))
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when (tl_out.d.fire()) {
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when (refill_one_beat) {
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accruedRefillError := refillError
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// clear bit when refill starts so hit-under-miss doesn't fetch bad data
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vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), refill_done && !invalidated)
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@ -205,8 +214,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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def wordMatch(addr: UInt) = addr.extract(log2Ceil(tl_out.d.bits.data.getWidth/8)-1, log2Ceil(wordBits/8)) === i
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def row(addr: UInt) = addr(untagBits-1, blockOffBits-log2Ceil(refillCycles))
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val s0_ren = (s0_valid && wordMatch(s0_vaddr)) || (s0_slaveValid && wordMatch(s0_slaveAddr))
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val wen = (tl_out.d.fire() && !invalidated) || (s3_slaveValid && wordMatch(s1s3_slaveAddr))
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val mem_idx = Mux(tl_out.d.fire(), (refill_idx << log2Ceil(refillCycles)) | refill_cnt,
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val wen = (refill_one_beat && !invalidated) || (s3_slaveValid && wordMatch(s1s3_slaveAddr))
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val mem_idx = Mux(refill_one_beat, (refill_idx << log2Ceil(refillCycles)) | refill_cnt,
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Mux(s3_slaveValid, row(s1s3_slaveAddr),
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Mux(s0_slaveValid, row(s0_slaveAddr),
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row(s0_vaddr))))
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@ -295,17 +304,43 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
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tl.e.ready := true
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}
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}
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tl_out.a.valid := s2_miss && !refill_valid
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tl_out.a.bits := edge_out.Get(
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fromSource = UInt(0),
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toAddress = (refill_addr >> blockOffBits) << blockOffBits,
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lgSize = lgCacheBlockBytes)._2
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if (cacheParams.prefetch) {
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val (crosses_page, next_block) = Split(refill_addr(pgIdxBits-1, blockOffBits) +& 1, pgIdxBits-blockOffBits)
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when (tl_out.a.fire()) {
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send_hint := !hint_outstanding && io.s2_prefetch && !crosses_page
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when (send_hint) {
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send_hint := false
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hint_outstanding := true
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}
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}
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when (refill_done) {
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send_hint := false
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}
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when (tl_out.d.fire() && !refill_one_beat) {
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hint_outstanding := false
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}
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when (send_hint) {
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tl_out.a.valid := true
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tl_out.a.bits := edge_out.Hint(
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fromSource = UInt(1),
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toAddress = Cat(refill_addr >> pgIdxBits, next_block) << blockOffBits,
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lgSize = lgCacheBlockBytes,
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param = TLHints.PREFETCH_READ)._2
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}
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}
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tl_out.b.ready := Bool(true)
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tl_out.c.valid := Bool(false)
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tl_out.e.valid := Bool(false)
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assert(!(tl_out.a.valid && addrMaybeInScratchpad(tl_out.a.bits.address)))
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when (!refill_valid) { invalidated := false.B }
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when (tl_out.a.fire()) { refill_valid := true.B }
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when (refill_fire) { refill_valid := true.B }
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when (refill_done) { refill_valid := false.B}
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}
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@ -49,6 +49,7 @@ class TLBResp(implicit p: Parameters) extends CoreBundle()(p) {
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val ae = new TLBExceptions
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val ma = new TLBExceptions
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val cacheable = Bool()
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val prefetchable = Bool()
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}
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class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(p) {
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@ -113,6 +114,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
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def fastCheck(member: TLManagerParameters => Boolean) =
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legal_address && edge.manager.fastProperty(mpu_physaddr, member, (b:Boolean) => Bool(b))
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val cacheable = fastCheck(_.supportsAcquireB)
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val homogeneous = TLBPageLookup(edge.manager.managers, xLen, p(CacheBlockBytes), BigInt(1) << pgIdxBits)(mpu_physaddr).homogeneous
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val prot_r = fastCheck(_.supportsGet) && pmp.io.r
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val prot_w = fastCheck(_.supportsPutFull) && pmp.io.w
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val prot_al = fastCheck(_.supportsLogical) || cacheable
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@ -181,6 +183,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
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val pal_array = Cat(Fill(2, prot_al), entries.init.map(_.pal).asUInt)
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val eff_array = Cat(Fill(2, prot_eff), entries.init.map(_.eff).asUInt)
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val c_array = Cat(Fill(2, cacheable), entries.init.map(_.c).asUInt)
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val prefetchable_array = Cat(cacheable && homogeneous, false.B, entries.init.map(_.c).asUInt)
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val misaligned = (io.req.bits.vaddr & (UIntToOH(io.req.bits.size) - 1)).orR
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val bad_va = vm_enabled &&
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@ -226,6 +229,7 @@ class TLB(lgMaxSize: Int, nEntries: Int)(implicit edge: TLEdgeOut, p: Parameters
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io.resp.ma.st := (ma_st_array & hits).orR
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io.resp.ma.inst := false // this is up to the pipeline to figure out
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io.resp.cacheable := (c_array & hits).orR
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io.resp.prefetchable := (prefetchable_array & hits).orR && edge.manager.managers.forall(m => !m.supportsAcquireB || m.supportsHint)
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io.resp.miss := do_refill || tlb_miss || multipleHits
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io.resp.paddr := Cat(ppn, pgOffset)
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