riscv/rocket-chip
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Merge pull request #918 from freechipsproject/icache-prefetch

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Icache prefetch
This commit is contained in:
Andrew Waterman
2017-08-02 21:22:20 -07:00
committed by GitHub
parent d66e8f8e80 2537d0d54e
commit 1be1433f04
3 changed files with 48 additions and 8 deletions
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src/main/scala/rocket/Frontend.scala
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@ -141,6 +141,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
icache.io.s2_vaddr := s2_pc
icache.io.s1_kill := s2_redirect || tlb.io.resp.miss || s2_replay
icache.io.s2_kill := s2_speculative && !s2_tlb_resp.cacheable || s2_xcpt
icache.io.s2_prefetch := s2_tlb_resp.prefetchable
fq.io.enq.valid := s2_valid && (icache.io.resp.valid || !s2_tlb_resp.miss && icache.io.s2_kill)
fq.io.enq.bits.pc := s2_pc