riscv/rocket-chip
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Remove unused CoreName parameter

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This commit is contained in:
Andrew Waterman 2016-08-09 15:24:59 -07:00
parent 458520c8f6
commit 1b8f919db2
1 changed files with 2 additions and 5 deletions
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7
rocket/src/main/scala/tile.scala
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@ -9,7 +9,6 @@ import uncore.devices._
import Util._ import Util._
import cde.{Parameters, Field} import cde.{Parameters, Field}
case object CoreName extends Field[String]
case object BuildRoCC extends Field[Seq[RoccParameters]] case object BuildRoCC extends Field[Seq[RoccParameters]]
case object NCachedTileLinkPorts extends Field[Int] case object NCachedTileLinkPorts extends Field[Int]
case object NUncachedTileLinkPorts extends Field[Int] case object NUncachedTileLinkPorts extends Field[Int]
@ -42,10 +41,8 @@ class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
val nRocc = buildRocc.size val nRocc = buildRocc.size
val nFPUPorts = buildRocc.filter(_.useFPU).size val nFPUPorts = buildRocc.filter(_.useFPU).size
val core = Module(new Rocket()(p.alterPartial({ case CoreName => "Rocket" }))) val core = Module(new Rocket)
val icache = Module(new Frontend()(p.alterPartial({ val icache = Module(new Frontend()(p.alterPartial({ case CacheName => "L1I" })))
case CacheName => "L1I"
case CoreName => "Rocket" })))
val dcache = val dcache =
if (p(NMSHRs) == 0) Module(new DCache()(dcacheParams)).io if (p(NMSHRs) == 0) Module(new DCache()(dcacheParams)).io
else Module(new HellaCache()(dcacheParams)).io else Module(new HellaCache()(dcacheParams)).io