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Add test for external TL clients (bus mastering)

This commit is contained in:
Howard Mao 2016-08-18 14:25:55 -07:00
parent 18982d7351
commit 1b6fa70b5c
3 changed files with 184 additions and 42 deletions

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@ -0,0 +1,108 @@
package groundtest
import Chisel._
import uncore.tilelink._
import uncore.agents._
import uncore.coherence.{InnerTLId, OuterTLId}
import uncore.Util._
import junctions.HasAddrMapParameters
import cde.Parameters
class ExampleBusMaster(implicit val p: Parameters) extends Module
with HasAddrMapParameters
with HasTileLinkParameters {
val mmioParams = p.alterPartial({ case TLId => p(InnerTLId) })
val memParams = p.alterPartial({ case TLId => p(OuterTLId) })
val memStart = addrMap("mem").start
val memStartBlock = memStart >> p(CacheBlockOffsetBits)
val io = new Bundle {
val mmio = new ClientUncachedTileLinkIO()(mmioParams).flip
val mem = new ClientUncachedTileLinkIO()(memParams)
}
val s_idle :: s_put :: s_resp :: Nil = Enum(Bits(), 3)
val state = Reg(init = s_idle)
val send_resp = Reg(init = Bool(false))
val r_acq = Reg(new AcquireMetadata)
io.mmio.acquire.ready := !send_resp
io.mmio.grant.valid := send_resp
io.mmio.grant.bits := Grant(
is_builtin_type = Bool(true),
g_type = r_acq.getBuiltInGrantType(),
client_xact_id = r_acq.client_xact_id,
manager_xact_id = UInt(0),
addr_beat = r_acq.addr_beat,
data = Mux(state === s_idle, UInt(0), UInt(1)))
when (io.mmio.acquire.fire()) {
send_resp := Bool(true)
r_acq := io.mmio.acquire.bits
when (state === s_idle && io.mmio.acquire.bits.hasData()) { state := s_put }
}
when (io.mmio.grant.fire()) { send_resp := Bool(false) }
val (put_beat, put_done) = Counter(io.mem.acquire.fire(), tlDataBeats)
when (put_done) { state := s_resp }
when (io.mem.grant.fire()) { state := s_idle }
io.mem.acquire.valid := state === s_put
io.mem.acquire.bits := PutBlock(
client_xact_id = UInt(0),
addr_block = UInt(memStartBlock),
addr_beat = put_beat,
data = put_beat)
io.mem.grant.ready := state === s_resp
}
class BusMasterTest(implicit p: Parameters) extends GroundTest()(p)
with HasTileLinkParameters {
val (s_idle :: s_req_start :: s_resp_start :: s_req_poll :: s_resp_poll ::
s_req_check :: s_resp_check :: s_done :: Nil) = Enum(Bits(), 8)
val state = Reg(init = s_idle)
val busMasterBlock = addrMap("io:ext:busmaster").start >> p(CacheBlockOffsetBits)
val start_acq = Put(
client_xact_id = UInt(0),
addr_block = UInt(busMasterBlock),
addr_beat = UInt(0),
data = UInt(1))
val poll_acq = Get(
client_xact_id = UInt(0),
addr_block = UInt(busMasterBlock),
addr_beat = UInt(0))
val check_acq = GetBlock(
client_xact_id = UInt(0),
addr_block = UInt(memStartBlock))
val acq = io.mem.head.acquire
val gnt = io.mem.head.grant
acq.valid := state.isOneOf(s_req_start, s_req_poll, s_req_check)
acq.bits := MuxLookup(state, check_acq, Seq(
s_req_start -> start_acq,
s_req_poll -> poll_acq))
gnt.ready := state.isOneOf(s_resp_start, s_resp_poll, s_resp_check)
val (get_beat, get_done) = Counter(
state === s_resp_check && gnt.valid, tlDataBeats)
when (state === s_idle) { state := s_req_start }
when (state === s_req_start && acq.ready) { state := s_resp_start }
when (state === s_resp_start && gnt.valid) { state := s_req_poll }
when (state === s_req_poll && acq.ready) { state := s_resp_poll }
when (state === s_resp_poll && gnt.valid) {
when (gnt.bits.data === UInt(0)) {
state := s_req_check
} .otherwise { state := s_req_poll }
}
when (state === s_req_check && acq.ready) { state := s_resp_check }
when (get_done) { state := s_done }
io.status.finished := state === s_done
assert(state =/= s_resp_check || !gnt.valid ||
gnt.bits.data === get_beat,
"BusMasterTest: data does not match")
}

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@ -9,6 +9,7 @@ import uncore.tilelink._
import uncore.devices._
import uncore.util._
import uncore.converters._
import uncore.coherence.{InnerTLId, OuterTLId}
import rocket._
import coreplex._
@ -240,7 +241,12 @@ class Periphery(implicit val p: Parameters) extends Module
Some(io.clients_out(client_ind - 1))
} else None
device.builder(mmioPort, clientPort, io.extra, p)
val buildParams = p.alterPartial({
case InnerTLId => "L2toMMIO"
case OuterTLId => "L1toL2"
})
device.builder(mmioPort, clientPort, io.extra, buildParams)
}
val ext = p(ExtMMIOPorts).map(

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@ -37,6 +37,54 @@ class WithUnitTest extends Config(
case _ => throw new CDEMatchError
})
class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
class WithGroundTest extends Config(
(pname, site, here) => pname match {
case BuildCoreplex => (p: Parameters) => Module(new GroundTestCoreplex(p))
case TLKey("L1toL2") => {
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
TileLinkParameters(
coherencePolicy = (
if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
else new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = site(NExternalClients) + site(NUncachedTileLinkPorts),
maxClientXacts = ((site(NMSHRs) + 1) +:
site(GroundTestKey).map(_.maxXacts))
.reduce(max(_, _)),
maxClientsPerPort = 1,
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBeats = 8,
dataBits = site(CacheBlockBytes)*8)
}
case BuildTiles => {
val groundtest = if (site(XLen) == 64)
DefaultTestSuites.groundtest64
else
DefaultTestSuites.groundtest32
TestGeneration.addSuite(groundtest("p"))
TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
(0 until site(NTiles)).map { i =>
val tileSettings = site(GroundTestKey)(i)
(r: Bool, p: Parameters) => {
Module(new GroundTestTile(resetSignal = r)(p.alterPartial({
case TLId => "L1toL2"
case GroundTestId => i
case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0
case NUncachedTileLinkPorts => tileSettings.uncached
})))
}
}
}
case UseFPU => false
case UseAtomics => false
case UseCompressed => false
case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
case _ => throw new CDEMatchError
})
class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)
class ComparatorConfig extends Config(
@ -78,8 +126,6 @@ class FancyNastiConverterTestConfig extends Config(
new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
new WithL2Cache ++ new GroundTestConfig)
class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
class TraceGenConfig extends Config(
new WithNCores(2) ++ new WithTraceGen ++ new GroundTestConfig)
class TraceGenBufferlessConfig extends Config(
@ -129,48 +175,30 @@ class DirectMemtestFPGAConfig extends Config(
class DirectComparatorFPGAConfig extends Config(
new FPGAConfig ++ new DirectComparatorConfig)
class WithGroundTest extends Config(
class WithBusMasterTest extends Config(
(pname, site, here) => pname match {
case BuildCoreplex => (p: Parameters) => Module(new GroundTestCoreplex(p))
case TLKey("L1toL2") => {
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
TileLinkParameters(
coherencePolicy = (
if (useMEI) new MEICoherence(site(L2DirectoryRepresentation))
else new MESICoherence(site(L2DirectoryRepresentation))),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
nCachingClients = site(NCachedTileLinkPorts),
nCachelessClients = site(NUncachedTileLinkPorts),
maxClientXacts = ((site(NMSHRs) + 1) +:
site(GroundTestKey).map(_.maxXacts))
.reduce(max(_, _)),
maxClientsPerPort = 1,
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBeats = 8,
dataBits = site(CacheBlockBytes)*8)
case GroundTestKey => Seq.fill(site(NTiles)) {
GroundTestTileSettings(uncached = 1)
}
case BuildTiles => {
val groundtest = if (site(XLen) == 64)
DefaultTestSuites.groundtest64
else
DefaultTestSuites.groundtest32
TestGeneration.addSuite(groundtest("p"))
TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
(0 until site(NTiles)).map { i =>
val tileSettings = site(GroundTestKey)(i)
(r: Bool, p: Parameters) => {
Module(new GroundTestTile(resetSignal = r)(p.alterPartial({
case TLId => "L1toL2"
case GroundTestId => i
case NCachedTileLinkPorts => if(tileSettings.cached > 0) 1 else 0
case NUncachedTileLinkPorts => tileSettings.uncached
})))
case BuildGroundTest =>
(p: Parameters) => Module(new BusMasterTest()(p))
case ExtraDevices => {
class BusMasterDevice extends Device {
def hasClientPort = true
def hasMMIOPort = true
def builder(
mmioPort: Option[ClientUncachedTileLinkIO],
clientPort: Option[ClientUncachedTileLinkIO],
extra: Bundle, p: Parameters) {
val busmaster = Module(new ExampleBusMaster()(p))
busmaster.io.mmio <> mmioPort.get
clientPort.get <> busmaster.io.mem
}
override def addrMapEntry =
AddrMapEntry("busmaster", MemSize(4096, MemAttr(AddrMapProt.RW)))
}
Seq(new BusMasterDevice)
}
case UseFPU => false
case UseAtomics => false
case UseCompressed => false
case RegressionTestNames => LinkedHashSet("rv64ui-p-simple")
case _ => throw new CDEMatchError
})
class BusMasterTestConfig extends Config(new WithBusMasterTest ++ new GroundTestConfig)