riscv/rocket-chip
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initial attempt at upgrade

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This commit is contained in:
Henry Cook
2013-08-12 10:39:11 -07:00
parent de313d97de
commit 1a9e43aa11
22 changed files with 921 additions and 908 deletions
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36
rocket/src/main/scala/util.scala
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@ -5,17 +5,17 @@ import scala.math._
object Util
{
implicit def intToUFix(x: Int): UFix = UFix(x)
implicit def intToUInt(x: Int): UInt = UInt(x)
implicit def intToBoolean(x: Int): Boolean = if (x != 0) true else false
implicit def booleanToInt(x: Boolean): Int = if (x) 1 else 0
implicit def booleanToBool(x: Boolean): Bits = Bool(x)
implicit def wcToUFix(c: WideCounter): UFix = c.value
implicit def wcToUInt(c: WideCounter): UInt = c.value
}
object AVec
{
def apply[T <: Data](elts: Seq[T]): Vec[T] = Vec(elts) { elts.head.clone }
def apply[T <: Data](elts: Seq[T]): Vec[T] = Vec(elts)
def apply[T <: Data](elts: Vec[T]): Vec[T] = apply(elts.toSeq)
def apply[T <: Data](elt0: T, elts: T*): Vec[T] = apply(elt0 :: elts.toList)
@ -38,9 +38,9 @@ object Str
require(validChar(x))
Lit(x, 8){Bits()}
}
def apply(x: UFix): Bits = apply(x, 10)
def apply(x: UFix, radix: Int): Bits = {
val rad = UFix(radix)
def apply(x: UInt): Bits = apply(x, 10)
def apply(x: UInt, radix: Int): Bits = {
val rad = UInt(radix)
val digs = digits(radix)
val w = x.getWidth
require(w > 0)
@ -49,18 +49,18 @@ object Str
var s = digs(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux(Bool(radix == 10) && q === UFix(0), Str(' '), digs(q % rad)), s)
s = Cat(Mux(Bool(radix == 10) && q === UInt(0), Str(' '), digs(q % rad)), s)
}
s
}
def apply(x: Fix): Bits = apply(x, 10)
def apply(x: Fix, radix: Int): Bits = {
val neg = x < Fix(0)
def apply(x: SInt): Bits = apply(x, 10)
def apply(x: SInt, radix: Int): Bits = {
val neg = x < SInt(0)
val abs = x.abs
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = UFix(radix)
val rad = UInt(radix)
val digs = digits(radix)
val w = abs.getWidth
require(w > 0)
@ -70,7 +70,7 @@ object Str
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === UFix(0)
val placeSpace = q === UInt(0)
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digs(q % rad)), s)
@ -117,21 +117,21 @@ case class WideCounter(width: Int, inc: Bool = Bool(true))
{
private val isWide = width >= 4
private val smallWidth = if (isWide) log2Up(width) else width
private val small = Reg(resetVal = UFix(0, smallWidth))
private val nextSmall = small + UFix(1, smallWidth+1)
private val small = RegReset(UInt(0, smallWidth))
private val nextSmall = small + UInt(1, smallWidth+1)
when (inc) { small := nextSmall(smallWidth-1,0) }
private val large = if (isWide) {
val r = Reg(resetVal = UFix(0, width - smallWidth))
when (inc && nextSmall(smallWidth)) { r := r + UFix(1) }
val r = RegReset(UInt(0, width - smallWidth))
when (inc && nextSmall(smallWidth)) { r := r + UInt(1) }
r
} else null
val value = Cat(large, small)
def := (x: UFix) = {
def := (x: UInt) = {
val w = x.getWidth
small := x(w.min(smallWidth)-1,0)
if (isWide) large := (if (w < smallWidth) UFix(0) else x(w.min(width)-1,smallWidth))
if (isWide) large := (if (w < smallWidth) UInt(0) else x(w.min(width)-1,smallWidth))
}
}