Vectorize ROCC and Tile memory interfaces
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@ -718,7 +718,6 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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require(isPow2(nSets))
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require(isPow2(nWays)) // TODO: relax this
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require(rowBits <= outerDataBits)
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require(paddrBits-blockOffBits == outerAddrBits)
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require(untagBits <= pgIdxBits)
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val wb = Module(new WritebackUnit)
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