riscv/rocket-chip
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Vectorize ROCC and Tile memory interfaces

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Henry Cook committed 2015-10-20 15:02:24 -07:00
1 parent 6f8997bee9
commit 1a1185be3f
6 files changed
+41 -41
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rocket/src/main/scala/icache.scala
-1
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@@ -7,7 +7,6 @@ import Util._
trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
val outerDataBeats = p(TLKey(p(TLId))).dataBeats
val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
val outerAddrBits = p(TLKey(p(TLId))).addrBits
val refillCyclesPerBeat = outerDataBits/rowBits
val refillCycles = refillCyclesPerBeat*outerDataBeats
}