Vectorize ROCC and Tile memory interfaces

2015-10-20 15:02:24 -07:00
parent 6f8997bee9
commit 1a1185be3f
6 changed files with 41 additions and 41 deletions
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@ -7,7 +7,6 @@ import Util._
 trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {
  val outerDataBeats = p(TLKey(p(TLId))).dataBeats
  val outerDataBits = p(TLKey(p(TLId))).dataBitsPerBeat
-  val outerAddrBits = p(TLKey(p(TLId))).addrBits
  val refillCyclesPerBeat = outerDataBits/rowBits
  val refillCycles = refillCyclesPerBeat*outerDataBeats
 }