riscv/rocket-chip
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Vectorize ROCC and Tile memory interfaces

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This commit is contained in:
Henry Cook
2015-10-20 15:02:24 -07:00
parent 6f8997bee9
commit 1a1185be3f
6 changed files with 41 additions and 41 deletions
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2
rocket/src/main/scala/csr.scala
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@ -131,7 +131,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
val reg_fflags = Reg(UInt(width = 5))
val reg_frm = Reg(UInt(width = 3))
val irq_rocc = Bool(!p(BuildRoCC).isEmpty) && io.rocc.interrupt
val irq_rocc = Bool(usingRoCC) && io.rocc.interrupt
io.interrupt_cause := 0
io.interrupt := io.interrupt_cause(xLen-1)