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don't use latches on mem ports for fpga

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Scott Beamer 2014-09-22 16:42:33 -07:00 committed by Yunsup Lee
parent f4e6cd75ab
commit 1a101f8de5
1 changed files with 1 additions and 1 deletions
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fsim/fpga_mem_gen
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@ -6,7 +6,7 @@
import sys
import math
use_latches = 1
use_latches = False
module_template = '''module %s(