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l1tol2: put a flow Q on the exits (#606)

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This Xbar connects the largest components in the design; the cores
and the L2 banks. We already have a full buffer on the core side.
However, the valid path going to the L2 comes back as a ready path.
Putting a flow Q also on the outputs of the l1tol2 cuts this path
in half at no cost to IPC.
This commit is contained in:
Wesley W. Terpstra 2017-03-23 16:28:32 -07:00 committed by GitHub
parent 055b8ba1f0
commit 19eb9b6906
1 changed files with 1 additions and 1 deletions
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src/main/scala/coreplex/CoreplexNetwork.scala
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@ -130,7 +130,7 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
val node = TLOutputNode() val node = TLOutputNode()
for (bank <- 0 until l2Config.nBanksPerChannel) { for (bank <- 0 until l2Config.nBanksPerChannel) {
val offset = (bank * l2Config.nMemoryChannels) + channel val offset = (bank * l2Config.nMemoryChannels) + channel
in := l1tol2.node in := TLBuffer(BufferParams.flow)(l1tol2.node)
node := TLFilter(AddressSet(offset * l1tol2_lineBytes, mask))(out) node := TLFilter(AddressSet(offset * l1tol2_lineBytes, mask))(out)
} }
node node