riscv/rocket-chip
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Fold uncore constants into TileLinkConfiguration, update coherence API

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This commit is contained in:
Henry Cook 2013-08-02 15:02:09 -07:00
parent c1b1a21a0f
commit 199e76fc77
5 changed files with 106 additions and 110 deletions
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2
riscv-rocket

@ -1 +1 @@
Subproject commit 3aa1971c855f3562f2d71cf824ecbb8ae41867fd
Subproject commit ee815dd3983f3b1a67fd3d810a513e23bdef97e4

103
src/main/scala/RocketChip.scala
View File

@ -8,13 +8,16 @@ import ReferenceChipBackend._
import scala.collection.mutable.ArrayBuffer
import scala.collection.mutable.HashMap
object DummyTopLevelConstants extends uncore.constants.CoherenceConfigConstants {
object DummyTopLevelConstants {
val NTILES = 2
val NBANKS = 1
val HTIF_WIDTH = 16
val ENABLE_SHARING = true
val ENABLE_CLEAN_EXCLUSIVE = true
val HAS_VEC = true
val NL2_REL_XACTS = 1
val NL2_ACQ_XACTS = 8
val NMSHRS = 2
}
object ReferenceChipBackend {
@ -75,37 +78,31 @@ class ReferenceChipBackend extends VerilogBackend
class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component
{
implicit val lnconf = conf.ln
implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2)
val io = new Bundle {
val tiles = Vec(conf.ln.nClients) { new TileLinkIO }.flip
val tiles = Vec(conf.nTiles) { new TileLinkIO }.flip
val htif = (new TileLinkIO).flip
val incoherent = Vec(conf.ln.nClients) { Bool() }.asInput
val incoherent = Vec(ln.nClients) { Bool() }.asInput
val mem = new ioMem
val mem_backup = new ioMemSerialized(htif_width)
val mem_backup_en = Bool(INPUT)
val mem = new ioMem
}
val lnWithHtifConf = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1,
idBits = log2Up(conf.ln.nEndpoints+1)+1,
nClients = conf.ln.nClients+1)
val ucWithHtifConf = conf.copy(ln = lnWithHtifConf)
require(clientEndpoints.length == lnWithHtifConf.nClients)
val masterEndpoints = (0 until lnWithHtifConf.nMasters).map(new L2CoherenceAgent(_)(ucWithHtifConf))
val incoherentWithHtif = io.incoherent :+ Bool(true)
val llc_tag_leaf = Mem(512, seqRead = true) { Bits(width = 152) }
val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf)
//val llc = new DRAMSideLLCNull(NGLOBAL_XACTS, REFILL_CYCLES)
//val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf)
val llc = new DRAMSideLLCNull(8, REFILL_CYCLES)
val mem_serdes = new MemSerdes(htif_width)
val net = new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)(ucWithHtifConf)
require(clientEndpoints.length == ln.nClients)
val masterEndpoints = (0 until ln.nMasters).map(new L2CoherenceAgent(_))
val net = new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)
net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
masterEndpoints.map{ _.io.incoherent zip incoherentWithHtif map { case (m, c) => m := c } }
masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
if(lnWithHtifConf.nMasters > 1) {
val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
val conv = new MemIOUncachedTileLinkIOConverter(2)
if(ln.nMasters > 1) {
val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters)
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out
} else {
@ -139,39 +136,39 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
io.mem_backup <> mem_serdes.io.narrow
}
case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int)
class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component
{
implicit val lnconf = conf.ln
implicit val tl = conf.tl
val io = new Bundle {
val debug = new DebugIO()
val host = new HostIO(htif_width)
val mem = new ioMem
val tiles = Vec(conf.nTiles) { new TileLinkIO }.flip
val htif = Vec(conf.nTiles) { new HTIFIO(conf.nTiles) }.flip
val incoherent = Vec(conf.nTiles) { Bool() }.asInput
val mem_backup = new ioMemSerialized(htif_width)
val mem_backup_en = Bool(INPUT)
val mem = new ioMem
val tiles = Vec(conf.ln.nClients) { new TileLinkIO }.flip
val htif = Vec(conf.ln.nClients) { new HTIFIO(conf.ln.nClients) }.flip
val incoherent = Vec(conf.ln.nClients) { Bool() }.asInput
}
val nBanks = 1
val bankIdLsb = 5
val htif = new rocketHTIF(htif_width)
val htif = new RocketHTIF(htif_width)
val outmemsys = new OuterMemorySystem(htif_width, tileList :+ htif)
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif
htif.io.cpu <> io.htif
outmemsys.io.incoherent <> io.incoherent
io.mem <> outmemsys.io.mem
outmemsys.io.mem <> io.mem
outmemsys.io.mem_backup_en <> io.mem_backup_en
// Add networking headers and endpoint queues
def convertAddrToBank(addr: Bits): UFix = {
require(bankIdLsb + log2Up(nBanks) < PADDR_BITS - OFFSET_BITS, {println("Invalid bits for bank multiplexing.")})
addr(bankIdLsb + log2Up(nBanks) - 1, bankIdLsb)
require(conf.bankIdLsb + log2Up(conf.nBanks) < MEM_ADDR_BITS, {println("Invalid bits for bank multiplexing.")})
addr(conf.bankIdLsb + log2Up(conf.nBanks) - 1, conf.bankIdLsb)
}
(outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map {
case ((outer, client), i) =>
outer.acquire <> TileLinkHeaderAppender(client.acquire, i, nBanks, convertAddrToBank _)
outer.release <> TileLinkHeaderAppender(client.release, i, nBanks, convertAddrToBank _)
outer.acquire <> TileLinkHeaderAppender(client.acquire, i, conf.nBanks, convertAddrToBank _)
outer.release <> TileLinkHeaderAppender(client.release, i, conf.nBanks, convertAddrToBank _)
val grant_ack_q = Queue(client.grant_ack)
outer.grant_ack.valid := grant_ack_q.valid
@ -211,15 +208,18 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
io.host.clk_edge := Reg(io.host.clk && !Reg(io.host.clk))
}
class TopIO(htif_width: Int) extends Bundle {
val debug = new rocket.DebugIO
val host = new rocket.HostIO(htif_width);
class TopIO(htifWidth: Int) extends Bundle {
val debug = new DebugIO
val host = new HostIO(htifWidth)
val mem = new ioMem
}
class VLSITopIO(htifWidth: Int) extends TopIO(htifWidth) {
val mem_backup_en = Bool(INPUT)
val in_mem_ready = Bool(OUTPUT)
val in_mem_valid = Bool(INPUT)
val out_mem_ready = Bool(INPUT)
val out_mem_valid = Bool(OUTPUT)
val mem = new ioMem
}
import DummyTopLevelConstants._
@ -240,22 +240,25 @@ class Top extends Component {
else new MICoherence
}
implicit val lnConf = LogicalNetworkConfiguration(NTILES+NBANKS, log2Up(NTILES)+1, NBANKS, NTILES)
implicit val uConf = UncoreConfiguration(co, lnConf)
implicit val ln = LogicalNetworkConfiguration(NTILES+NBANKS+1, log2Up(NTILES)+1, NBANKS, NTILES+1)
implicit val tl = TileLinkConfiguration(co, ln, log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS), 2*log2Up(NMSHRS*NTILES+1), MEM_DATA_BITS)
implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5)
val io = new TopIO(HTIF_WIDTH)
val resetSigs = Vec(NTILES){ Bool() }
val ic = ICacheConfig(128, 2, co, ntlb = 8, nbtb = 16)
val dc = DCacheConfig(128, 4, co, ntlb = 8,
nmshr = 2, nrpq = 16, nsdq = 17)
val rc = RocketConfiguration(lnConf, co, ic, dc,
val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16)
val dc = DCacheConfig(128, 4, ntlb = 8,
nmshr = NMSHRS, nrpq = 16, nsdq = 17, states = co.nClientStates)
val rc = RocketConfiguration(tl, ic, dc,
fpu = true, vec = HAS_VEC)
val tileList = (0 until NTILES).map(r => new Tile(resetSignal = resetSigs(r))(rc))
val io = new VLSITopIO(HTIF_WIDTH)
val resetSigs = Vec(uc.nTiles){Bool()}
val tileList = (0 until uc.nTiles).map(r => new Tile(resetSignal = resetSigs(r))(rc))
val uncore = new Uncore(HTIF_WIDTH, tileList)
var error_mode = Bool(false)
for (i <- 0 until NTILES) {
for (i <- 0 until uc.nTiles) {
val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i)
val il = uncore.io.incoherent(i)

82
src/main/scala/fpga.scala
View File

@ -7,28 +7,24 @@ import rocket._
class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component
{
implicit val lnconf = conf.ln
implicit val (tl, ln, l2) = (conf.tl, conf.tl.ln, conf.l2)
val io = new Bundle {
val tiles = Vec(conf.ln.nClients) { new TileLinkIO }.flip
val tiles = Vec(conf.nTiles) { new TileLinkIO }.flip
val htif = (new TileLinkIO).flip
val incoherent = Vec(conf.ln.nClients) { Bool() }.asInput
val incoherent = Vec(ln.nClients) { Bool() }.asInput
val mem = new ioMem
}
val lnWithHtifConf = conf.ln.copy(nEndpoints = conf.ln.nEndpoints+1,
idBits = log2Up(conf.ln.nEndpoints+1)+1,
nClients = conf.ln.nClients+1)
val ucWithHtifConf = conf.copy(ln = lnWithHtifConf)
require(clientEndpoints.length == lnWithHtifConf.nClients)
val masterEndpoints = (0 until lnWithHtifConf.nMasters).map(new L2CoherenceAgent(_)(ucWithHtifConf))
require(clientEndpoints.length == ln.nClients)
val masterEndpoints = (0 until ln.nMasters).map(new L2CoherenceAgent(_))
val net = new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)(ucWithHtifConf)
val net = new ReferenceChipCrossbarNetwork(masterEndpoints++clientEndpoints)
net.io zip (masterEndpoints.map(_.io.client) ++ io.tiles :+ io.htif) map { case (net, end) => net <> end }
masterEndpoints.map{ _.io.incoherent zip (io.incoherent ++ List(Bool(true))) map { case (m, c) => m := c } }
masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
val conv = new MemIOUncachedTileLinkIOConverter(2)(ucWithHtifConf)
if(lnWithHtifConf.nMasters > 1) {
val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(lnWithHtifConf.nMasters, conf.co)(lnWithHtifConf)
val conv = new MemIOUncachedTileLinkIOConverter(2)
if(ln.nMasters > 1) {
val arb = new UncachedTileLinkIOArbiterThatAppendsArbiterId(ln.nMasters)
arb.io.in zip masterEndpoints.map(_.io.master) map { case (arb, cache) => arb <> cache }
conv.io.uncached <> arb.io.out
} else {
@ -41,35 +37,31 @@ class FPGAOuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenc
class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Component
{
implicit val lnconf = conf.ln
implicit val (tl, ln) = (conf.tl, conf.tl.ln)
val io = new Bundle {
val debug = new DebugIO()
val host = new HostIO(htif_width)
val mem = new ioMem
val tiles = Vec(conf.ln.nClients) { new TileLinkIO }.flip
val htif = Vec(conf.ln.nClients) { new HTIFIO(conf.ln.nClients) }.flip
val incoherent = Vec(conf.ln.nClients) { Bool() }.asInput
val tiles = Vec(conf.nTiles) { new TileLinkIO }.flip
val htif = Vec(conf.nTiles) { new HTIFIO(conf.nTiles) }.flip
val incoherent = Vec(conf.nTiles) { Bool() }.asInput
}
val nBanks = 1
val bankIdLsb = 5
val htif = new rocketHTIF(htif_width)
val htif = new RocketHTIF(htif_width)
val outmemsys = new FPGAOuterMemorySystem(htif_width, tileList :+ htif)
htif.io.cpu <> io.htif
outmemsys.io.incoherent <> io.incoherent
io.mem <> outmemsys.io.mem
outmemsys.io.mem <> io.mem
// Add networking headers and endpoint queues
// Add networking headers and endpoint queues
def convertAddrToBank(addr: Bits): UFix = {
require(bankIdLsb + log2Up(nBanks) < PADDR_BITS - OFFSET_BITS, {println("Invalid bits for bank multiplexing.")})
addr(bankIdLsb + log2Up(nBanks) - 1, bankIdLsb)
require(conf.bankIdLsb + log2Up(conf.nBanks) < MEM_ADDR_BITS, {println("Invalid bits for bank multiplexing.")})
addr(conf.bankIdLsb + log2Up(conf.nBanks) - 1, conf.bankIdLsb)
}
outmemsys.io.incoherent <> (io.incoherent :+ Bool(true))
(outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map {
case ((outer, client), i) =>
outer.acquire <> TileLinkHeaderAppender(client.acquire, i, nBanks, convertAddrToBank _)
outer.release <> TileLinkHeaderAppender(client.release, i, nBanks, convertAddrToBank _)
outer.acquire <> TileLinkHeaderAppender(client.acquire, i, conf.nBanks, convertAddrToBank _)
outer.release <> TileLinkHeaderAppender(client.release, i, conf.nBanks, convertAddrToBank _)
val grant_ack_q = Queue(client.grant_ack)
outer.grant_ack.valid := grant_ack_q.valid
@ -85,31 +77,33 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
htif.io.host.in <> io.host.in
}
class FPGATopIO(htifWidth: Int) extends TopIO(htifWidth)
class FPGATop extends Component {
val htif_width = 16
val io = new Bundle {
val debug = new DebugIO
val host = new HostIO(htif_width)
val mem = new ioMem
}
val co = new MESICoherence
val ntiles = 1
val nbanks = 1
implicit val lnConf = LogicalNetworkConfiguration(ntiles+nbanks, log2Up(ntiles)+1, nbanks, ntiles)
implicit val uconf = UncoreConfiguration(co, lnConf)
val nmshrs = 2
implicit val ln = LogicalNetworkConfiguration(ntiles+nbanks+1, log2Up(ntiles)+1, nbanks, ntiles+1)
implicit val tl = TileLinkConfiguration(co, ln, log2Up(1+8), 2*log2Up(nmshrs*ntiles+1), MEM_DATA_BITS)
implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8)
implicit val uc = UncoreConfiguration(l2, tl, ntiles, nbanks, bankIdLsb = 5)
val resetSigs = Vec(uconf.ln.nClients){ Bool() }
val ic = ICacheConfig(64, 1, co, ntlb = 4, nbtb = 4)
val dc = DCacheConfig(64, 1, co, ntlb = 4,
nmshr = 2, nrpq = 16, nsdq = 17)
val rc = RocketConfiguration(uconf.ln, co, ic, dc,
val ic = ICacheConfig(64, 1, ntlb = 4, nbtb = 4)
val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, states = co.nClientStates)
val rc = RocketConfiguration(tl, ic, dc,
fastMulDiv = false,
fpu = false, vec = false)
val tileList = (0 until uconf.ln.nClients).map(r => new Tile(resetSignal = resetSigs(r))(rc))
val uncore = new FPGAUncore(htif_width = htif_width, tileList = tileList)
val io = new FPGATopIO(htif_width)
val resetSigs = Vec(uc.nTiles){Bool()}
val tileList = (0 until uc.nTiles).map(r => new Tile(resetSignal = resetSigs(r))(rc))
val uncore = new FPGAUncore(htif_width, tileList)
io.debug.error_mode := Bool(false)
for (i <- 0 until uconf.ln.nClients) {
for (i <- 0 until uc.nTiles) {
val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i)
val il = uncore.io.incoherent(i)

27
src/main/scala/network.scala
View File

@ -5,19 +5,19 @@ import uncore._
import scala.reflect._
object TileLinkHeaderAppender {
def apply[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasMemData](in: ClientSourcedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(implicit conf: UncoreConfiguration) = {
def apply[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](in: ClientSourcedDataIO[LogicalNetworkIO[T],LogicalNetworkIO[U]], clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(implicit conf: TileLinkConfiguration) = {
val shim = new TileLinkHeaderAppender(clientId, nBanks, addrConvert)(in.meta.bits.payload.clone, in.data.bits.payload.clone)
shim.io.in <> in
shim.io.out
}
def apply[T <: SourcedMessage with HasPhysicalAddress](in: ClientSourcedFIFOIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(implicit conf: UncoreConfiguration) = {
def apply[T <: SourcedMessage with HasPhysicalAddress](in: ClientSourcedFIFOIO[LogicalNetworkIO[T]], clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(implicit conf: TileLinkConfiguration) = {
val shim = new TileLinkHeaderAppender(clientId, nBanks, addrConvert)(in.bits.payload.clone, new AcquireData)
shim.io.in.meta <> in
shim.io.out.meta
}
}
class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasMemData](clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(metadata: => T, data: => U)(implicit conf: UncoreConfiguration) extends Component {
class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: SourcedMessage with HasTileLinkData](clientId: Int, nBanks: Int, addrConvert: Bits => UFix)(metadata: => T, data: => U)(implicit conf: TileLinkConfiguration) extends Component {
implicit val ln = conf.ln
val io = new Bundle {
val in = new ClientSourcedDataIO()((new LogicalNetworkIO){ metadata }, (new LogicalNetworkIO){ data }).flip
@ -68,8 +68,7 @@ class TileLinkHeaderAppender[T <: SourcedMessage with HasPhysicalAddress, U <: S
}
//Adapter betweewn an UncachedTileLinkIO and a mem controller MemIO
class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: UncoreConfiguration) extends Component {
implicit val ln = conf.ln
class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: TileLinkConfiguration) extends Component {
val io = new Bundle {
val uncached = new UncachedTileLinkIO().flip
val mem = new ioMem
@ -94,10 +93,10 @@ class MemIOUncachedTileLinkIOConverter(qDepth: Int)(implicit conf: UncoreConfigu
io.mem.req_data <> mem_data_q.io.deq
}
class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf.ln) {
implicit val lnConf = conf.ln
class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit conf: UncoreConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf.tl.ln) {
implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkIO).flip}; case h:MasterCoherenceAgent => {new TileLinkIO}})){ new TileLinkIO }
implicit val pconf = new PhysicalNetworkConfiguration(conf.ln.nEndpoints, conf.ln.idBits) // Same config for all networks
implicit val pconf = new PhysicalNetworkConfiguration(ln.nEndpoints, ln.idBits) // Same config for all networks
// Aliases for the various network IO bundle types
type FBCIO[T <: Data] = FIFOIO[PhysicalNetworkIO[T]]
@ -119,12 +118,12 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
}
def CrossbarToMasterShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
val out = DefaultFromCrossbarShim(in)
out.bits.header.src := in.bits.header.src - UFix(conf.ln.nMasters)
out.bits.header.src := in.bits.header.src - UFix(ln.nMasters)
out
}
def CrossbarToClientShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
val out = DefaultFromCrossbarShim(in)
out.bits.header.dst := in.bits.header.dst - UFix(conf.ln.nMasters)
out.bits.header.dst := in.bits.header.dst - UFix(ln.nMasters)
out
}
def DefaultToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
@ -137,12 +136,12 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
}
def MasterToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
val out = DefaultToCrossbarShim(in)
out.bits.header.dst := in.bits.header.dst + UFix(conf.ln.nMasters)
out.bits.header.dst := in.bits.header.dst + UFix(ln.nMasters)
out
}
def ClientToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
val out = DefaultToCrossbarShim(in)
out.bits.header.src := in.bits.header.src + UFix(conf.ln.nMasters)
out.bits.header.src := in.bits.header.src + UFix(ln.nMasters)
out
}
@ -203,11 +202,11 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
// Actually instantiate the particular networks required for TileLink
def acqHasData(acq: PhysicalNetworkIO[Acquire]) = conf.co.messageHasData(acq.payload)
def acqHasData(acq: PhysicalNetworkIO[Acquire]) = co.messageHasData(acq.payload)
val acq_net = new PairedCrossbar(REFILL_CYCLES, acqHasData _)(new Acquire, new AcquireData)
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, acq_net.io.in(id), acq_net.io.out(id), io.acquire) }
def relHasData(rel: PhysicalNetworkIO[Release]) = conf.co.messageHasData(rel.payload)
def relHasData(rel: PhysicalNetworkIO[Release]) = co.messageHasData(rel.payload)
val rel_net = new PairedCrossbar(REFILL_CYCLES, relHasData _)(new Release, new ReleaseData)
endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => doClientSourcedPairedHookup(end, rel_net.io.in(id), rel_net.io.out(id), io.release) }

2
uncore

@ -1 +1 @@
Subproject commit a456695526f4d2b35d017841b4fe14d2ba97d8f4
Subproject commit 0f675e35e7503419482b12fb265ef2709a91403a