riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

diplomacy: provide connect access to edges without bundles

Browse Source 
Forcing the bundles to exist early can mess up module ownership.
This commit is contained in:
Wesley W. Terpstra 2017-05-16 20:51:55 -07:00
parent 65053978dc
commit 191dad7800
2 changed files with 13 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/main/scala/diplomacy/Nodes.scala
View File

@ -18,8 +18,8 @@ trait InwardNodeImp[DI, UI, EI, BI <: Data]
def bundleI(ei: EI): BI def bundleI(ei: EI): BI
def colour: String def colour: String
def reverse: Boolean = false def reverse: Boolean = false
def connect(bindings: () => Seq[(EI, BI, BI)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { def connect(edges: () => Seq[EI], bundles: () => Seq[(EI, BI, BI)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
(None, () => bindings().foreach { case (_, i, o) => i <> o }) (None, () => bundles().foreach { case (_, i, o) => i <> o })
} }
// optional methods to track node graph // optional methods to track node graph
@ -244,7 +244,13 @@ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
case BIND_STAR => BIND_QUERY case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR }) case BIND_QUERY => BIND_STAR })
x.iPush(o, y, binding) x.iPush(o, y, binding)
def bindings() = { def edges() = {
val (iStart, iEnd) = x.iPortMapping(i)
val (oStart, oEnd) = y.oPortMapping(o)
require (iEnd - iStart == oEnd - oStart, s"Bug in diplomacy; ${iEnd-iStart} != ${oEnd-oStart} means port resolution failed")
Seq.tabulate(iEnd - iStart) { j => x.edgesIn(iStart+j) }
}
def bundles() = {
val (iStart, iEnd) = x.iPortMapping(i) val (iStart, iEnd) = x.iPortMapping(i)
val (oStart, oEnd) = y.oPortMapping(o) val (oStart, oEnd) = y.oPortMapping(o)
require (iEnd - iStart == oEnd - oStart, s"Bug in diplomacy; ${iEnd-iStart} != ${oEnd-oStart} means port resolution failed") require (iEnd - iStart == oEnd - oStart, s"Bug in diplomacy; ${iEnd-iStart} != ${oEnd-oStart} means port resolution failed")
@ -252,7 +258,7 @@ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
(x.edgesIn(iStart+j), x.bundleIn(iStart+j), y.bundleOut(oStart+j)) (x.edgesIn(iStart+j), x.bundleIn(iStart+j), y.bundleOut(oStart+j))
} }
} }
val (out, newbinding) = inner.connect(bindings _) val (out, newbinding) = inner.connect(edges _, bundles _)
LazyModule.stack.head.bindings = newbinding :: LazyModule.stack.head.bindings LazyModule.stack.head.bindings = newbinding :: LazyModule.stack.head.bindings
out out
} }

6
src/main/scala/uncore/tilelink2/Nodes.scala
View File

@ -25,10 +25,10 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
override def labelI(ei: TLEdgeIn) = (ei.manager.beatBytes * 8).toString override def labelI(ei: TLEdgeIn) = (ei.manager.beatBytes * 8).toString
override def labelO(eo: TLEdgeOut) = (eo.manager.beatBytes * 8).toString override def labelO(eo: TLEdgeOut) = (eo.manager.beatBytes * 8).toString
override def connect(bindings: () => Seq[(TLEdgeIn, TLBundle, TLBundle)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = { override def connect(edges: () => Seq[TLEdgeIn], bundles: () => Seq[(TLEdgeIn, TLBundle, TLBundle)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
val monitor = p(TLMonitorBuilder)(TLMonitorArgs(() => bindings().map(_._1), sourceInfo, p)) val monitor = p(TLMonitorBuilder)(TLMonitorArgs(edges, sourceInfo, p))
(monitor, () => { (monitor, () => {
val eval = bindings () val eval = bundles ()
monitor.foreach { m => (eval zip m.module.io.in) foreach { case ((_,i,o), m) => m := TLBundleSnoop(o,i) } } monitor.foreach { m => (eval zip m.module.io.in) foreach { case ((_,i,o), m) => m := TLBundleSnoop(o,i) } }
eval.foreach { case (_, bi, bo) => eval.foreach { case (_, bi, bo) =>
bi <> bo bi <> bo