diplomacy: provide connect access to edges without bundles
Forcing the bundles to exist early can mess up module ownership.
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@ -18,8 +18,8 @@ trait InwardNodeImp[DI, UI, EI, BI <: Data]
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def bundleI(ei: EI): BI
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def colour: String
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def reverse: Boolean = false
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def connect(bindings: () => Seq[(EI, BI, BI)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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(None, () => bindings().foreach { case (_, i, o) => i <> o })
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def connect(edges: () => Seq[EI], bundles: () => Seq[(EI, BI, BI)])(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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(None, () => bundles().foreach { case (_, i, o) => i <> o })
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}
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// optional methods to track node graph
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@ -244,7 +244,13 @@ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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case BIND_STAR => BIND_QUERY
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case BIND_QUERY => BIND_STAR })
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x.iPush(o, y, binding)
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def bindings() = {
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def edges() = {
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val (iStart, iEnd) = x.iPortMapping(i)
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val (oStart, oEnd) = y.oPortMapping(o)
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require (iEnd - iStart == oEnd - oStart, s"Bug in diplomacy; ${iEnd-iStart} != ${oEnd-oStart} means port resolution failed")
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Seq.tabulate(iEnd - iStart) { j => x.edgesIn(iStart+j) }
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}
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def bundles() = {
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val (iStart, iEnd) = x.iPortMapping(i)
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val (oStart, oEnd) = y.oPortMapping(o)
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require (iEnd - iStart == oEnd - oStart, s"Bug in diplomacy; ${iEnd-iStart} != ${oEnd-oStart} means port resolution failed")
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@ -252,7 +258,7 @@ abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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(x.edgesIn(iStart+j), x.bundleIn(iStart+j), y.bundleOut(oStart+j))
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}
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}
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val (out, newbinding) = inner.connect(bindings _)
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val (out, newbinding) = inner.connect(edges _, bundles _)
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LazyModule.stack.head.bindings = newbinding :: LazyModule.stack.head.bindings
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out
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}
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