riscv/rocket-chip
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Update README.md to reflect firrtl and riscv-tools changes

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Andrew Waterman 2016-10-26 16:47:25 -07:00
parent 8c538f548b
commit 190a8b9dd3
1 changed files with 2 additions and 8 deletions
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README.md
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@ -38,7 +38,7 @@ of riscv-tools:
$ git submodule update --init --recursive $ git submodule update --init --recursive
$ export RISCV=/path/to/install/riscv/toolchain $ export RISCV=/path/to/install/riscv/toolchain
$ ./build.sh $ ./build.sh
$ ./build-rv32im.sh (if you are using RV32). $ ./build-rv32ima.sh (if you are using RV32).
For more information (or if you run into any issues), please consult the For more information (or if you run into any issues), please consult the
[riscv-tools/README](https://github.com/riscv/riscv-tools/blob/master/README.md). [riscv-tools/README](https://github.com/riscv/riscv-tools/blob/master/README.md).
@ -92,13 +92,7 @@ If riscv-tools version changes, you should recompile and install riscv-tools acc
$ cd riscv-tools $ cd riscv-tools
$ ./build.sh $ ./build.sh
$ ./build-rv32im.sh (if you are using RV32) $ ./build-rv32ima.sh (if you are using RV32)
If firrtl version changes and you are using Chisel3, you may need to clean and recompile:
$ cd firrtl
$ sbt clean
$ sbt assembly
## <a name="what"></a> What's in the Rocket chip generator repository? ## <a name="what"></a> What's in the Rocket chip generator repository?