riscv/rocket-chip
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put data can be used for ignts

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This commit is contained in:
Henry Cook 2015-03-18 18:28:03 -07:00
parent 1ff184bf62
commit 19059bf0eb
1 changed files with 2 additions and 1 deletions
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3
uncore/src/main/scala/cache.scala
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@ -638,7 +638,8 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
pending_ignt_data := pending_ignt_data | pending_ignt_data := pending_ignt_data |
addPendingBitInternal(io.data.resp) | addPendingBitInternal(io.data.resp) |
addPendingBitWhenHasData(io.inner.release) | addPendingBitWhenHasData(io.inner.release) |
addPendingBitWhenHasData(io.outer.grant) addPendingBitWhenHasData(io.outer.grant) |
addPendingBitWhenHasData(io.inner.acquire)
val ignt_q = Module(new Queue(new L2SecondaryMissInfo, nSecondaryMisses))(innerTLParams) val ignt_q = Module(new Queue(new L2SecondaryMissInfo, nSecondaryMisses))(innerTLParams)
val (ignt_data_idx, ignt_data_done) = connectOutgoingDataBeatCounter(io.inner.grant, ignt_q.io.deq.bits.addr_beat) val (ignt_data_idx, ignt_data_done) = connectOutgoingDataBeatCounter(io.inner.grant, ignt_q.io.deq.bits.addr_beat)
ignt_q.io.enq.valid := Bool(false) ignt_q.io.enq.valid := Bool(false)