riscv/rocket-chip
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don't use +verbose in vsim .run rule

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This commit is contained in:
Howard Mao 2016-05-04 23:01:14 -07:00
parent 8b06947446
commit 18ffe7b1ec
1 changed files with 1 additions and 1 deletions
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vsim/Makefrag-verilog
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@ -47,7 +47,7 @@ $(sim_dir)/dramsim2_ini:
ln -s $(base_dir)/emulator/dramsim2_ini $(sim_dir)/dramsim2_ini
$(output_dir)/%.run: $(output_dir)/% $(sim_dir)/dramsim2_ini $(simv)
cd $(sim_dir) && $(exec_simv) +dramsim +verbose +max-cycles=$(timeout_cycles) $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
cd $(sim_dir) && $(exec_simv) +dramsim +max-cycles=$(timeout_cycles) $< 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
$(output_dir)/%.out: $(output_dir)/% $(sim_dir)/dramsim2_ini $(simv)
cd $(sim_dir) && $(exec_simv) +dramsim +verbose +max-cycles=$(timeout_cycles) $< $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]