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tilelink2: make it possible to write Node-only adapters

This commit is contained in:
Wesley W. Terpstra 2016-08-31 16:45:18 -07:00
parent 4a401fc480
commit 18e7d4cd65
4 changed files with 36 additions and 0 deletions

View File

@ -28,3 +28,14 @@ class TLBuffer(entries: Int = 2, pipe: Boolean = false) extends LazyModule
}
})
}
object TLBuffer
{
// applied to the TL source node; connect (TLBuffer(x.node) -> y.node)
def apply(x: TLBaseNode, entries: Int = 2, pipe: Boolean = false)(implicit lazyModule: LazyModule): TLBaseNode = {
val buffer = new TLBuffer(entries, pipe)
lazyModule.addChild(buffer)
lazyModule.connect(x -> buffer.node)
buffer.node
}
}

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@ -72,3 +72,14 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
out.e.bits := in.e.bits
})
}
object TLHintHandler
{
// applied to the TL source node; connect (TLHintHandler(x.node) -> y.node)
def apply(x: TLBaseNode, supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit lazyModule: LazyModule): TLBaseNode = {
val hints = new TLHintHandler(supportManagers, supportClients, passthrough)
lazyModule.addChild(hints)
lazyModule.connect(x -> hints.node)
hints.node
}
}

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@ -9,6 +9,7 @@ import chisel3.internal.sourceinfo.SourceInfo
abstract class LazyModule
{
private val bindings = ListBuffer[() => Unit]()
private val extraChildren = ListBuffer[LazyModule]()
// Use as: connect(source -> sink, source2 -> sink2, ...)
def connect[PO, PI, EO, EI, B <: Bundle](edges: (BaseNode[PO, PI, EO, EI, B], BaseNode[PO, PI, EO, EI, B])*)(implicit sourceInfo: SourceInfo) = {
@ -25,13 +26,18 @@ abstract class LazyModule
if (m.getParameterTypes.isEmpty &&
!java.lang.reflect.Modifier.isStatic(m.getModifiers) &&
!(m.getName contains '$') &&
!(m.getName == "lazyModule") &&
classOf[LazyModule].isAssignableFrom(m.getReturnType)) {
// ... and force their lazy module members to exist
m.invoke(this).asInstanceOf[LazyModule].module
}
}
extraChildren.foreach { _.module }
bindings.foreach { f => f () }
}
implicit val lazyModule = this
def addChild(x: LazyModule) = extraChildren += x
}
abstract class LazyModuleImp(outer: LazyModule) extends Module

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@ -0,0 +1,8 @@
package uncore
import Chisel._
package object tilelink2
{
type TLBaseNode = BaseNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
}