tilelink2: make it possible to write Node-only adapters
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4a401fc480
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18e7d4cd65
@ -28,3 +28,14 @@ class TLBuffer(entries: Int = 2, pipe: Boolean = false) extends LazyModule
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}
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})
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}
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object TLBuffer
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{
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// applied to the TL source node; connect (TLBuffer(x.node) -> y.node)
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def apply(x: TLBaseNode, entries: Int = 2, pipe: Boolean = false)(implicit lazyModule: LazyModule): TLBaseNode = {
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val buffer = new TLBuffer(entries, pipe)
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lazyModule.addChild(buffer)
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lazyModule.connect(x -> buffer.node)
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buffer.node
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}
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}
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@ -72,3 +72,14 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
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out.e.bits := in.e.bits
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})
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}
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object TLHintHandler
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{
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// applied to the TL source node; connect (TLHintHandler(x.node) -> y.node)
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def apply(x: TLBaseNode, supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit lazyModule: LazyModule): TLBaseNode = {
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val hints = new TLHintHandler(supportManagers, supportClients, passthrough)
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lazyModule.addChild(hints)
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lazyModule.connect(x -> hints.node)
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hints.node
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}
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}
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@ -9,6 +9,7 @@ import chisel3.internal.sourceinfo.SourceInfo
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abstract class LazyModule
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{
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private val bindings = ListBuffer[() => Unit]()
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private val extraChildren = ListBuffer[LazyModule]()
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// Use as: connect(source -> sink, source2 -> sink2, ...)
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def connect[PO, PI, EO, EI, B <: Bundle](edges: (BaseNode[PO, PI, EO, EI, B], BaseNode[PO, PI, EO, EI, B])*)(implicit sourceInfo: SourceInfo) = {
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@ -25,13 +26,18 @@ abstract class LazyModule
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if (m.getParameterTypes.isEmpty &&
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!java.lang.reflect.Modifier.isStatic(m.getModifiers) &&
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!(m.getName contains '$') &&
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!(m.getName == "lazyModule") &&
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classOf[LazyModule].isAssignableFrom(m.getReturnType)) {
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// ... and force their lazy module members to exist
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m.invoke(this).asInstanceOf[LazyModule].module
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}
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}
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extraChildren.foreach { _.module }
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bindings.foreach { f => f () }
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}
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implicit val lazyModule = this
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def addChild(x: LazyModule) = extraChildren += x
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}
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abstract class LazyModuleImp(outer: LazyModule) extends Module
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8
uncore/src/main/scala/tilelink2/package.scala
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8
uncore/src/main/scala/tilelink2/package.scala
Normal file
@ -0,0 +1,8 @@
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package uncore
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import Chisel._
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package object tilelink2
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{
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type TLBaseNode = BaseNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
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}
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