Error device: require explicit control of atomic and transfer sizes

src/main/scala/amba/axi4/Fragmenter.scala

@@ -67,6 +67,7 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
         val alignment = hi(AXI4Parameters.lenBits-1,0)
 
         // We don't care about illegal addresses; bursts or no bursts... whatever circuit is simpler (AXI4ToTL will fix it)
+        // !!! think about this more -- what if illegal?
         val sizes1 = (supportedSizes1 zip slave.slaves.map(_.address)).filter(_._1 >= 0).groupBy(_._1).mapValues(_.flatMap(_._2))
         val reductionMask = AddressDecoder(sizes1.values.toList)
         val support1 = Mux1H(sizes1.toList.map { case (v, a) => // maximum supported size-1 based on target address

src/main/scala/amba/axi4/Test.scala

@@ -98,7 +98,7 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends SimpleLazyModule with HasF
   val node = AXI4IdentityNode()
   val xbar = LazyModule(new TLXbar)
   val ram  = LazyModule(new TLRAM(fuzzAddr))
-  val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)), maxTransfer = 256)))
+  val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)), maxAtomic = 8, maxTransfer = 256)))
 
   ram.node   := TLErrorEvaluator(pattern) := TLFragmenter(4, 16) := xbar.node
   error.node := xbar.node

src/main/scala/coreplex/Configs.scala

@@ -24,7 +24,7 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
   case PeripheryBusKey => PeripheryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
   case MemoryBusKey => MemoryBusParams(beatBytes = site(XLen)/8, blockBytes = site(CacheBlockBytes))
   // Additional device Parameters
-  case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)))
+  case ErrorParams => ErrorParams(Seq(AddressSet(0x3000, 0xfff)), maxAtomic=site(XLen)/8, maxTransfer=4096)
   case BootROMParams => BootROMParams(contentFileName = "./bootrom/bootrom.img")
   case DebugModuleParams => DefaultDebugModuleParams(site(XLen))
 })

src/main/scala/devices/tilelink/BusBypass.scala

@@ -18,8 +18,9 @@ abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false)(implic
 
   protected val bar = LazyModule(new TLBusBypassBar)
   protected val everything = Seq(AddressSet(0, BigInt("ffffffffffffffffffffffffffffffff", 16))) // 128-bit
-  protected val error = if (deadlock) LazyModule(new DeadlockDevice(ErrorParams(everything), beatBytes))
+  protected val params = ErrorParams(everything, maxAtomic=16, maxTransfer=4096)
-                        else LazyModule(new TLError(ErrorParams(everything), beatBytes))
+  protected val error = if (deadlock) LazyModule(new DeadlockDevice(params, beatBytes))
+                        else LazyModule(new TLError(params, beatBytes))
 
   // order matters
   bar.node := nodeIn

src/main/scala/devices/tilelink/Error.scala

@@ -10,13 +10,18 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 import scala.math.min
 
-case class ErrorParams(address: Seq[AddressSet], maxTransfer: Int = 4096)
+case class ErrorParams(address: Seq[AddressSet], maxAtomic: Int, maxTransfer: Int)
+{
+  require (1 <= maxAtomic && maxAtomic <= maxTransfer && maxTransfer <= 4096)
+}
+
 case object ErrorParams extends Field[ErrorParams]
 
 abstract class DevNullDevice(params: ErrorParams, beatBytes: Int = 4)
                             (device: SimpleDevice)
                             (implicit p: Parameters) extends LazyModule {
   val xfer = TransferSizes(1, params.maxTransfer)
+  val atom = TransferSizes(1, params.maxAtomic)
   val node = TLManagerNode(Seq(TLManagerPortParameters(
     Seq(TLManagerParameters(
       address            = params.address,
@@ -28,8 +33,8 @@ abstract class DevNullDevice(params: ErrorParams, beatBytes: Int = 4)
       supportsGet        = xfer,
       supportsPutPartial = xfer,
       supportsPutFull    = xfer,
-      supportsArithmetic = xfer,
+      supportsArithmetic = atom,
-      supportsLogical    = xfer,
+      supportsLogical    = atom,
       supportsHint       = xfer,
       fifoId             = Some(0))), // requests are handled in order
     beatBytes  = beatBytes,