Error device: require explicit control of atomic and transfer sizes
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@ -10,13 +10,18 @@ import freechips.rocketchip.tilelink._
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import freechips.rocketchip.util._
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import scala.math.min
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case class ErrorParams(address: Seq[AddressSet], maxTransfer: Int = 4096)
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case class ErrorParams(address: Seq[AddressSet], maxAtomic: Int, maxTransfer: Int)
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{
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require (1 <= maxAtomic && maxAtomic <= maxTransfer && maxTransfer <= 4096)
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}
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case object ErrorParams extends Field[ErrorParams]
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abstract class DevNullDevice(params: ErrorParams, beatBytes: Int = 4)
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(device: SimpleDevice)
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(implicit p: Parameters) extends LazyModule {
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val xfer = TransferSizes(1, params.maxTransfer)
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val atom = TransferSizes(1, params.maxAtomic)
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val node = TLManagerNode(Seq(TLManagerPortParameters(
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Seq(TLManagerParameters(
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address = params.address,
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@ -28,8 +33,8 @@ abstract class DevNullDevice(params: ErrorParams, beatBytes: Int = 4)
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supportsGet = xfer,
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supportsPutPartial = xfer,
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supportsPutFull = xfer,
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supportsArithmetic = xfer,
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supportsLogical = xfer,
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supportsArithmetic = atom,
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supportsLogical = atom,
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supportsHint = xfer,
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fifoId = Some(0))), // requests are handled in order
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beatBytes = beatBytes,
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