riscv/rocket-chip
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Error device: require explicit control of atomic and transfer sizes

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This commit is contained in:
Wesley W. Terpstra
2017-12-08 13:41:09 -08:00
parent 6a0150aad7
commit 18b8a61775
5 changed files with 14 additions and 7 deletions
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5
src/main/scala/devices/tilelink/BusBypass.scala
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@ -18,8 +18,9 @@ abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false)(implic
protected val bar = LazyModule(new TLBusBypassBar)
protected val everything = Seq(AddressSet(0, BigInt("ffffffffffffffffffffffffffffffff", 16))) // 128-bit
protected val error = if (deadlock) LazyModule(new DeadlockDevice(ErrorParams(everything), beatBytes))
else LazyModule(new TLError(ErrorParams(everything), beatBytes))
protected val params = ErrorParams(everything, maxAtomic=16, maxTransfer=4096)
protected val error = if (deadlock) LazyModule(new DeadlockDevice(params, beatBytes))
else LazyModule(new TLError(params, beatBytes))
// order matters
bar.node := nodeIn