riscv/rocket-chip
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Error device: require explicit control of atomic and transfer sizes

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This commit is contained in:
Wesley W. Terpstra
2017-12-08 13:41:09 -08:00
parent 6a0150aad7
commit 18b8a61775
5 changed files with 14 additions and 7 deletions
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5
src/main/scala/devices/tilelink/BusBypass.scala
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@ -18,8 +18,9 @@ abstract class TLBusBypassBase(beatBytes: Int, deadlock: Boolean = false)(implic
protected val bar = LazyModule(new TLBusBypassBar)
protected val everything = Seq(AddressSet(0, BigInt("ffffffffffffffffffffffffffffffff", 16))) // 128-bit
protected val error = if (deadlock) LazyModule(new DeadlockDevice(ErrorParams(everything), beatBytes))
else LazyModule(new TLError(ErrorParams(everything), beatBytes))
protected val params = ErrorParams(everything, maxAtomic=16, maxTransfer=4096)
protected val error = if (deadlock) LazyModule(new DeadlockDevice(params, beatBytes))
else LazyModule(new TLError(params, beatBytes))
// order matters
bar.node := nodeIn

11
src/main/scala/devices/tilelink/Error.scala
View File

@ -10,13 +10,18 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import scala.math.min
case class ErrorParams(address: Seq[AddressSet], maxTransfer: Int = 4096)
case class ErrorParams(address: Seq[AddressSet], maxAtomic: Int, maxTransfer: Int)
{
require (1 <= maxAtomic && maxAtomic <= maxTransfer && maxTransfer <= 4096)
}
case object ErrorParams extends Field[ErrorParams]
abstract class DevNullDevice(params: ErrorParams, beatBytes: Int = 4)
(device: SimpleDevice)
(implicit p: Parameters) extends LazyModule {
val xfer = TransferSizes(1, params.maxTransfer)
val atom = TransferSizes(1, params.maxAtomic)
val node = TLManagerNode(Seq(TLManagerPortParameters(
Seq(TLManagerParameters(
address = params.address,
@ -28,8 +33,8 @@ abstract class DevNullDevice(params: ErrorParams, beatBytes: Int = 4)
supportsGet = xfer,
supportsPutPartial = xfer,
supportsPutFull = xfer,
supportsArithmetic = xfer,
supportsLogical = xfer,
supportsArithmetic = atom,
supportsLogical = atom,
supportsHint = xfer,
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,