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Error device: require explicit control of atomic and transfer sizes

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This commit is contained in:
Wesley W. Terpstra
2017-12-08 13:41:09 -08:00
parent 6a0150aad7
commit 18b8a61775
5 changed files with 14 additions and 7 deletions
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1
src/main/scala/amba/axi4/Fragmenter.scala
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@ -67,6 +67,7 @@ class AXI4Fragmenter()(implicit p: Parameters) extends LazyModule
val alignment = hi(AXI4Parameters.lenBits-1,0)
// We don't care about illegal addresses; bursts or no bursts... whatever circuit is simpler (AXI4ToTL will fix it)
// !!! think about this more -- what if illegal?
val sizes1 = (supportedSizes1 zip slave.slaves.map(_.address)).filter(_._1 >= 0).groupBy(_._1).mapValues(_.flatMap(_._2))
val reductionMask = AddressDecoder(sizes1.values.toList)
val support1 = Mux1H(sizes1.toList.map { case (v, a) => // maximum supported size-1 based on target address

2
src/main/scala/amba/axi4/Test.scala
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@ -98,7 +98,7 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends SimpleLazyModule with HasF
val node = AXI4IdentityNode()
val xbar = LazyModule(new TLXbar)
val ram = LazyModule(new TLRAM(fuzzAddr))
val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)), maxTransfer = 256)))
val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)), maxAtomic = 8, maxTransfer = 256)))
ram.node := TLErrorEvaluator(pattern) := TLFragmenter(4, 16) := xbar.node
error.node := xbar.node