Move store data generation into cache

2013-09-14 16:15:07 -07:00
parent a0cb711451
commit 18968dfbc7
3 changed files with 21 additions and 23 deletions
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@ -245,7 +245,7 @@ class FPToInt extends Module
  }

  io.out.valid := valid
-  io.out.bits.store := Mux(in.single, Cat(unrec_s, unrec_s), unrec_d)
+  io.out.bits.store := Mux(in.single, Cat(unrec_d(63,32), unrec_s), unrec_d)
  io.out.bits.lt := dcmp.io.a_lt_b
 }