riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

move junctions utils into top-level utils package

Browse Source
This commit is contained in:
Howard Mao
2016-09-13 20:22:20 -07:00
parent 7dd4492abb
commit 1882241493
25 changed files with 293 additions and 267 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/rocket/dcache.scala
View File

@ -127,11 +127,11 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
meta.io.read <> metaReadArb.io.out
meta.io.write <> metaWriteArb.io.out
val s1_meta = meta.io.resp
val s1_hit_way = s1_meta.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt
val s1_hit_state = ClientMetadata.onReset.fromBits(
val s1_meta_hit_way = s1_meta.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt
val s1_meta_hit_state = ClientMetadata.onReset.fromBits(
s1_meta.map(r => Mux(r.tag === s1_tag, r.coh.asUInt, UInt(0)))
.reduce (_|_))
(s1_hit_way, s1_hit_state, s1_meta(s1_victim_way))
(s1_meta_hit_way, s1_meta_hit_state, s1_meta(s1_victim_way))
}
val s1_data_way = Mux(inWriteback, releaseWay, s1_hit_way)
val s1_data = Mux1H(s1_data_way, data.io.resp) // retime into s2 if critical