move junctions utils into top-level utils package

src/main/scala/rocket/arbiter.scala

@@ -4,7 +4,7 @@ package rocket
 
 import Chisel._
 import cde.{Parameters, Field}
-import junctions.{ParameterizedBundle, DecoupledHelper}
+import util.{ParameterizedBundle, DecoupledHelper}
 
 class HellaCacheArbiter(n: Int)(implicit p: Parameters) extends Module
 {

src/main/scala/rocket/btb.scala

@@ -3,11 +3,11 @@
 package rocket
 
 import Chisel._
-import junctions._
 import cde.{Parameters, Field}
 import Util._
 import uncore.util._
 import uncore.agents.PseudoLRU
+import util.ParameterizedBundle
 
 case object BtbKey extends Field[BtbParameters]
 

src/main/scala/rocket/dcache.scala

@@ -127,11 +127,11 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
       meta.io.read <> metaReadArb.io.out
       meta.io.write <> metaWriteArb.io.out
       val s1_meta = meta.io.resp
-      val s1_hit_way = s1_meta.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt
-      val s1_hit_state = ClientMetadata.onReset.fromBits(
+      val s1_meta_hit_way = s1_meta.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt
+      val s1_meta_hit_state = ClientMetadata.onReset.fromBits(
         s1_meta.map(r => Mux(r.tag === s1_tag, r.coh.asUInt, UInt(0)))
         .reduce (_|_))
-      (s1_hit_way, s1_hit_state, s1_meta(s1_victim_way))
+      (s1_meta_hit_way, s1_meta_hit_state, s1_meta(s1_victim_way))
     }
   val s1_data_way = Mux(inWriteback, releaseWay, s1_hit_way)
   val s1_data = Mux1H(s1_data_way, data.io.resp) // retime into s2 if critical

src/main/scala/rocket/ibuf.scala

@@ -5,7 +5,7 @@ package rocket
 import Chisel._
 import Util._
 import cde.{Parameters, Field}
-import junctions._
+import util.ParameterizedBundle
 
 class Instruction(implicit val p: Parameters) extends ParameterizedBundle with HasCoreParameters {
   val pf0 = Bool() // page fault on first half of instruction

src/main/scala/rocket/nbdcache.scala

@@ -3,12 +3,12 @@
 package rocket
 
 import Chisel._
-import junctions._
 import uncore.tilelink._
 import uncore.coherence._
 import uncore.agents._
 import uncore.util._
 import uncore.constants._
+import util.{ParameterizedBundle, DecoupledHelper}
 import cde.{Parameters, Field}
 import Util._
 
@@ -44,7 +44,7 @@ trait HasL1HellaCacheParameters extends HasL1CacheParameters {
 
 abstract class L1HellaCacheModule(implicit val p: Parameters) extends Module
   with HasL1HellaCacheParameters
-abstract class L1HellaCacheBundle(implicit val p: Parameters) extends junctions.ParameterizedBundle()(p)
+abstract class L1HellaCacheBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
   with HasL1HellaCacheParameters
 
 trait HasCoreMemOp extends HasCoreParameters {

src/main/scala/rocket/rocket.scala

@@ -3,10 +3,11 @@
 package rocket
 
 import Chisel._
-import junctions._
 import uncore.devices._
 import uncore.agents.CacheName
 import uncore.constants._
+import junctions.HasAddrMapParameters
+import util.ParameterizedBundle
 import Util._
 import cde.{Parameters, Field}