riscv/rocket-chip
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DTS tweaks (#740)

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* rocket: do not report 's' in isa string

* rocket: report the micro-architecture of the core
This commit is contained in:
Wesley W. Terpstra 2017-05-12 05:32:57 -07:00 committed by GitHub
parent a69fcd50dd
commit 18725a05b0
1 changed files with 2 additions and 3 deletions
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5
src/main/scala/rocket/Tile.scala
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@ -40,8 +40,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
val f = if (rocketParams.core.fpu.nonEmpty) "f" else "" val f = if (rocketParams.core.fpu.nonEmpty) "f" else ""
val d = if (rocketParams.core.fpu.nonEmpty && p(XLen) > 32) "d" else "" val d = if (rocketParams.core.fpu.nonEmpty && p(XLen) > 32) "d" else ""
val c = if (rocketParams.core.useCompressed) "c" else "" val c = if (rocketParams.core.useCompressed) "c" else ""
val s = if (rocketParams.core.useVM) "s" else "" val isa = s"rv${p(XLen)}i$m$a$f$d$c"
val isa = s"rv${p(XLen)}i$m$a$f$d$c$s"
val dcache = rocketParams.dcache.map(d => Map( val dcache = rocketParams.dcache.map(d => Map(
"d-cache-block-size" -> ofInt(block), "d-cache-block-size" -> ofInt(block),
@ -83,7 +82,7 @@ class RocketTile(val rocketParams: RocketTileParams, val hartid: Int)(implicit p
Description(s"cpus/cpu@${hartid}", Map( Description(s"cpus/cpu@${hartid}", Map(
"reg" -> resources("reg").map(_.value), "reg" -> resources("reg").map(_.value),
"device_type" -> ofStr("cpu"), "device_type" -> ofStr("cpu"),
"compatible" -> ofStr("riscv"), "compatible" -> Seq(ResourceString("sifive,rocket0"), ResourceString("riscv")),
"status" -> ofStr("okay"), "status" -> ofStr("okay"),
"clock-frequency" -> Seq(ResourceInt(rocketParams.core.bootFreqHz)), "clock-frequency" -> Seq(ResourceInt(rocketParams.core.bootFreqHz)),
"riscv,isa" -> ofStr(isa)) "riscv,isa" -> ofStr(isa))