diff --git a/src/main/scala/coreplex/FrontBus.scala b/src/main/scala/coreplex/FrontBus.scala
index 8a492c2d..ae791b4b 100644
--- a/src/main/scala/coreplex/FrontBus.scala
+++ b/src/main/scala/coreplex/FrontBus.scala
@@ -20,8 +20,12 @@ case object FrontBusParams extends Field[FrontBusParams]
 class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
   xbar.suggestName("FrontBus")
 
-  def fromSyncMasters(params: BufferParams = BufferParams.default, buffers: Int = 1): TLInwardNode = {
+  def fromSyncMasters(params: BufferParams = BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode =
+    fromSyncPorts(params, buffers, name)
+
+  def fromSyncPorts(params: BufferParams =  BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode = {
     val buf = List.fill(buffers)(LazyModule(new TLBuffer(params)))
+    name.foreach { n => buf.zipWithIndex foreach {case (b, i) => b.suggestName(s"FrontBus_${n}_${i}_TLBuffer")}}
     for(i<-1 until buffers) {
       buf(i).node :=* buf(i-1).node
     }
@@ -29,18 +33,8 @@ class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrap
     if(buffers>0) buf(0).node else inwardNode
   }
 
-  def fromSyncPorts(params: BufferParams =  BufferParams.default, buffers: Int = 1): TLInwardNode = {
-    val buf = List.fill(buffers)(LazyModule(new TLBuffer(params)))
-    for(i<-1 until buffers) {
-      buf(i).node :=* buf(i-1).node
-    }
-    inwardNode :=* buf(buffers-1).node
-    if(buffers>0) buf(0).node else inwardNode
-  }
-
-  def fromSyncFIFOMaster(params: BufferParams =  BufferParams.default, buffers: Int = 1): TLInwardNode = fromSyncPorts(params, buffers)
-
-
+  def fromSyncFIFOMaster(params: BufferParams =  BufferParams.default, buffers: Int = 1, name: Option[String] = None): TLInwardNode =
+    fromSyncPorts(params, buffers, name)
 
   def toSystemBus : TLOutwardNode = outwardBufNode
 
diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index bbbc45ff..0d37bc0c 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -52,27 +52,30 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def fromCoherentChip: TLInwardNode = inwardNode
 
-  def fromSyncTiles(params: BufferParams): TLInwardNode = {
+  def fromSyncTiles(params: BufferParams, name: Option[String] = None): TLInwardNode = {
     val buf = LazyModule(new TLBuffer(params))
+    name.foreach{n => buf.suggestName(s"SystemBus_${n}_TLBuffer")}
     tile_fixer.node :=* buf.node
     buf.node
   }
 
-  def fromRationalTiles(dir: RationalDirection): TLRationalInwardNode = {
+  def fromRationalTiles(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
     val sink = LazyModule(new TLRationalCrossingSink(direction = dir))
+    name.foreach{n => sink.suggestName(s"SystemBus_${n}_TLRationalCrossingSink")}
     tile_fixer.node :=* sink.node
     sink.node
   }
 
-  def fromAsyncTiles(depth: Int, sync: Int): TLAsyncInwardNode = {
+  def fromAsyncTiles(depth: Int, sync: Int, name: Option[String] = None): TLAsyncInwardNode = {
     val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
+    name.foreach{n => sink.suggestName(s"SystemBus_${n}_TLAsyncCrossingSink")}
     tile_fixer.node :=* sink.node
     sink.node
   }
 
   def fromSyncPorts(params: BufferParams =  BufferParams.default, name: Option[String] = None): TLInwardNode = {
     val buffer = LazyModule(new TLBuffer(params))
-    name.foreach{ n => buffer.suggestName(s"${n}_TLBuffer") }
+    name.foreach{ n => buffer.suggestName(s"SystemBus_${n}_TLBuffer") }
     port_fixer.node :=* buffer.node
     buffer.node
   }
@@ -81,21 +84,23 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
     fromSyncPorts(params, name)
   }
 
-  def fromAsyncPorts(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = {
+  def fromAsyncPorts(depth: Int = 8, sync: Int = 3, name : Option[String] = None): TLAsyncInwardNode = {
     val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
+    name.foreach{ n => sink.suggestName(s"SystemBus_${n}_TLAsyncCrossingSink") }
     port_fixer.node :=* sink.node
     sink.node
   }
 
-  def fromAsyncFIFOMaster(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = fromAsyncPorts(depth, sync)
+  def fromAsyncFIFOMaster(depth: Int = 8, sync: Int = 3, name: Option[String] = None): TLAsyncInwardNode = fromAsyncPorts(depth, sync, name)
 
-  def fromRationalPorts(dir: RationalDirection): TLRationalInwardNode = {
+  def fromRationalPorts(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = {
     val sink = LazyModule(new TLRationalCrossingSink(dir))
+    name.foreach{ n => sink.suggestName(s"SystemBus_${n}_TLRationalCrossingSink") }
     port_fixer.node :=* sink.node
     sink.node
   }
 
-  def fromRationalFIFOMaster(dir: RationalDirection): TLRationalInwardNode = fromRationalPorts(dir)
+  def fromRationalFIFOMaster(dir: RationalDirection, name: Option[String] = None): TLRationalInwardNode = fromRationalPorts(dir, name)
 }
 
 /** Provides buses that serve as attachment points,