From 17d404b325fa71f715f03356baa060386840a41d Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 15 Aug 2013 15:27:38 -0700 Subject: [PATCH] final Reg changes --- uncore/src/llc.scala | 28 ++++++++++++++-------------- uncore/src/memserdes.scala | 18 +++++++++--------- uncore/src/network.scala | 8 ++++---- uncore/src/slowio.scala | 12 ++++++------ uncore/src/uncore.scala | 32 ++++++++++++++++---------------- 5 files changed, 49 insertions(+), 49 deletions(-) diff --git a/uncore/src/llc.scala b/uncore/src/llc.scala index cd4341bb..f9907934 100644 --- a/uncore/src/llc.scala +++ b/uncore/src/llc.scala @@ -29,7 +29,7 @@ class BigMem[T <: Data](n: Int, preLatency: Int, postLatency: Int, leaf: Mem[UIn val wdata = in.bits.wdata.toBits val wmask = in.bits.wmask.toBits val ren = in.valid && !in.bits.rw - val reg_ren = RegUpdate(ren) + val reg_ren = Reg(next=ren) val rdata = Vec.fill(nWide){Bits()} val r = Pipe(ren, in.bits.addr, postLatency) @@ -113,7 +113,7 @@ class LLCMSHRFile(sets: Int, ways: Int, outstanding: Int) extends Module override def clone = new MSHR().asInstanceOf[this.type] } - val valid = Vec.fill(outstanding){RegReset(Bool(false))} + val valid = Vec.fill(outstanding){Reg(init=Bool(false))} val validBits = valid.toBits val freeId = PriorityEncoder(~validBits) val mshr = Vec.fill(outstanding){Reg(new MSHR)} @@ -191,12 +191,12 @@ class LLCWriteback(requestors: Int) extends Module val mem = new ioMemPipe } - val valid = RegReset(Bool(false)) + val valid = Reg(init=Bool(false)) val who = Reg(UInt()) val addr = Reg(UInt()) val cmd_sent = Reg(Bool()) val data_sent = Reg(Bool()) - val count = RegReset(UInt(0, log2Up(REFILL_CYCLES))) + val count = Reg(init=UInt(0, log2Up(REFILL_CYCLES))) var anyReq = Bool(false) for (i <- 0 until requestors) { @@ -252,10 +252,10 @@ class LLCData(latency: Int, sets: Int, ways: Int, leaf: Mem[UInt]) extends Modul } val q = Module(new Queue(new QEntry, latency+2)) val qReady = q.io.count <= UInt(q.entries-latency-1) - val valid = RegReset(Bool(false)) + val valid = Reg(init=Bool(false)) val req = Reg(io.req.bits.clone) - val count = RegReset(UInt(0, log2Up(REFILL_CYCLES))) - val refillCount = RegReset(UInt(0, log2Up(REFILL_CYCLES))) + val count = Reg(init=UInt(0, log2Up(REFILL_CYCLES))) + val refillCount = Reg(init=UInt(0, log2Up(REFILL_CYCLES))) when (data.io.in.valid && !io.mem_resp.valid) { count := count + UInt(1) @@ -307,7 +307,7 @@ class MemReqArb(n: Int) extends Module // UNTESTED val mem = new ioMem } - val lock = RegReset(Bool(false)) + val lock = Reg(init=Bool(false)) val locker = Reg(UInt()) val arb = Module(new RRArbiter(new MemReqCmd, n)) @@ -360,17 +360,17 @@ class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, tagLeaf: Mem[UInt], da val data = Module(new LLCData(4, sets, ways, dataLeaf)) val writeback = Module(new LLCWriteback(2)) - val initCount = RegReset(UInt(0, log2Up(sets+1))) + val initCount = Reg(init=UInt(0, log2Up(sets+1))) val initialize = !initCount(log2Up(sets)) when (initialize) { initCount := initCount + UInt(1) } - val replay_s2 = RegReset(Bool(false)) - val s2_valid = RegReset(Bool(false)) + val replay_s2 = Reg(init=Bool(false)) + val s2_valid = Reg(init=Bool(false)) val s2 = Reg(new MemReqCmd) val s3_rdy = Bool() val replay_s2_rdy = Bool() - val s1_valid = Reg(updateData = io.cpu.req_cmd.fire() || replay_s2 && replay_s2_rdy, resetData = Bool(false)) + val s1_valid = Reg(next = io.cpu.req_cmd.fire() || replay_s2 && replay_s2_rdy, init = Bool(false)) val s1 = Reg(new MemReqCmd) when (io.cpu.req_cmd.fire()) { s1 := io.cpu.req_cmd.bits } when (replay_s2 && replay_s2_rdy) { s1 := s2 } @@ -451,7 +451,7 @@ class HellaFlowQueue[T <: Data](val entries: Int)(data: => T) extends Module val do_enq = io.enq.fire() && !do_flow val do_deq = io.deq.fire() && !do_flow - val maybe_full = RegReset(Bool(false)) + val maybe_full = Reg(init=Bool(false)) val enq_ptr = Counter(do_enq, entries)._1 val deq_ptr = Counter(do_deq, entries)._1 when (do_enq != do_deq) { maybe_full := do_enq } @@ -509,7 +509,7 @@ class DRAMSideLLCNull(numRequests: Int, refillCycles: Int) extends Module val inc = Bool() val dec = Bool() - val count = RegReset(UInt(numEntries, size)) + val count = Reg(init=UInt(numEntries, size)) val watermark = count >= UInt(refillCycles) when (inc && !dec) { diff --git a/uncore/src/memserdes.scala b/uncore/src/memserdes.scala index 9badb5e9..7a021621 100644 --- a/uncore/src/memserdes.scala +++ b/uncore/src/memserdes.scala @@ -54,9 +54,9 @@ class MemSerdes(w: Int) extends Module val in_buf = Reg(Bits()) val s_idle :: s_read_addr :: s_write_addr :: s_write_idle :: s_write_data :: Nil = Enum(5) { UInt() } - val state = RegReset(s_idle) - val send_cnt = RegReset(UInt(0, log2Up((max(abits, dbits)+w-1)/w))) - val data_send_cnt = RegReset(UInt(0, log2Up(REFILL_CYCLES))) + val state = Reg(init=s_idle) + val send_cnt = Reg(init=UInt(0, log2Up((max(abits, dbits)+w-1)/w))) + val data_send_cnt = Reg(init=UInt(0, log2Up(REFILL_CYCLES))) val adone = io.narrow.req.ready && send_cnt === UInt((abits-1)/w) val ddone = io.narrow.req.ready && send_cnt === UInt((dbits-1)/w) @@ -96,9 +96,9 @@ class MemSerdes(w: Int) extends Module send_cnt := UInt(0) } - val recv_cnt = RegReset(UInt(0, log2Up((rbits+w-1)/w))) - val data_recv_cnt = RegReset(UInt(0, log2Up(REFILL_CYCLES))) - val resp_val = RegReset(Bool(false)) + val recv_cnt = Reg(init=UInt(0, log2Up((rbits+w-1)/w))) + val data_recv_cnt = Reg(init=UInt(0, log2Up(REFILL_CYCLES))) + val resp_val = Reg(init=Bool(false)) resp_val := Bool(false) when (io.narrow.resp.valid) { @@ -129,14 +129,14 @@ class MemDesser(w: Int) extends Module // test rig side val rbits = io.wide.resp.bits.getWidth require(dbits >= abits && rbits >= dbits) - val recv_cnt = RegReset(UInt(0, log2Up((rbits+w-1)/w))) - val data_recv_cnt = RegReset(UInt(0, log2Up(REFILL_CYCLES))) + val recv_cnt = Reg(init=UInt(0, log2Up((rbits+w-1)/w))) + val data_recv_cnt = Reg(init=UInt(0, log2Up(REFILL_CYCLES))) val adone = io.narrow.req.valid && recv_cnt === UInt((abits-1)/w) val ddone = io.narrow.req.valid && recv_cnt === UInt((dbits-1)/w) val rdone = io.narrow.resp.valid && recv_cnt === UInt((rbits-1)/w) val s_cmd_recv :: s_cmd :: s_data_recv :: s_data :: s_reply :: Nil = Enum(5) { UInt() } - val state = RegReset(s_cmd_recv) + val state = Reg(init=s_cmd_recv) val in_buf = Reg(Bits()) when (io.narrow.req.valid && io.narrow.req.ready || io.narrow.resp.valid) { diff --git a/uncore/src/network.scala b/uncore/src/network.scala index 8733e2a6..9de890b1 100644 --- a/uncore/src/network.scala +++ b/uncore/src/network.scala @@ -19,8 +19,8 @@ class PairedArbiterIO[M <: Data, D <: Data](n: Int)(m: => M, d: => D) extends Bu class PairedLockingRRArbiter[M <: Data, D <: Data](n: Int, count: Int, needsLock: Option[M => Bool] = None)(meta: => M, data: => D) extends Module { require(isPow2(count)) val io = new PairedArbiterIO(n)(meta,data) - val locked = if(count > 1) RegReset(Bool(false)) else Bool(false) - val lockIdx = if(count > 1) RegReset(UInt(n-1)) else UInt(n-1) + val locked = if(count > 1) Reg(init=Bool(false)) else Bool(false) + val lockIdx = if(count > 1) Reg(init=UInt(n-1)) else UInt(n-1) val grant = List.fill(n)(Bool()) val meta_chosen = Bits(width = log2Up(n)) @@ -37,7 +37,7 @@ class PairedLockingRRArbiter[M <: Data, D <: Data](n: Int, count: Int, needsLock io.data_chosen := Mux(locked, lockIdx, meta_chosen) if(count > 1){ - val cnt = RegReset(UInt(0, width = log2Up(count))) + val cnt = Reg(init=UInt(0, width = log2Up(count))) val cnt_next = cnt + UInt(1) when(io.out.data.fire()){ cnt := cnt_next @@ -54,7 +54,7 @@ class PairedLockingRRArbiter[M <: Data, D <: Data](n: Int, count: Int, needsLock } } } - val last_grant = RegReset(Bits(0, log2Up(n))) + val last_grant = Reg(init=Bits(0, log2Up(n))) val ctrl = ArbiterCtrl((0 until n).map(i => io.in(i).meta.valid && UInt(i) > last_grant) ++ io.in.map(_.meta.valid)) (0 until n).map(i => grant(i) := ctrl(i) && UInt(i) > last_grant || ctrl(i + n)) diff --git a/uncore/src/slowio.scala b/uncore/src/slowio.scala index 93c1324a..79c837d1 100644 --- a/uncore/src/slowio.scala +++ b/uncore/src/slowio.scala @@ -14,10 +14,10 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module } require(divisor_max >= 8 && divisor_max <= 65536 && isPow2(divisor_max)) - val divisor = RegReset(UInt(divisor_max-1)) - val d_shadow = RegReset(UInt(divisor_max-1)) - val hold = RegReset(UInt(divisor_max/4-1)) - val h_shadow = RegReset(UInt(divisor_max/4-1)) + val divisor = Reg(init=UInt(divisor_max-1)) + val d_shadow = Reg(init=UInt(divisor_max-1)) + val hold = Reg(init=UInt(divisor_max/4-1)) + val h_shadow = Reg(init=UInt(divisor_max/4-1)) when (io.set_divisor.valid) { d_shadow := io.set_divisor.bits(log2Up(divisor_max)-1, 0).toUInt h_shadow := io.set_divisor.bits(log2Up(divisor_max)-1+16, 16).toUInt @@ -42,8 +42,8 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module myclock := Bool(true) } - val in_slow_rdy = RegReset(Bool(false)) - val out_slow_val = RegReset(Bool(false)) + val in_slow_rdy = Reg(init=Bool(false)) + val out_slow_val = Reg(init=Bool(false)) val out_slow_bits = Reg(data) val fromhost_q = Module(new Queue(data,1)) diff --git a/uncore/src/uncore.scala b/uncore/src/uncore.scala index dde4190a..bfc703fa 100644 --- a/uncore/src/uncore.scala +++ b/uncore/src/uncore.scala @@ -96,11 +96,11 @@ abstract class XactTracker()(implicit conf: L2CoherenceAgentConfiguration) exten class VoluntaryReleaseTracker(trackerId: Int, bankId: Int)(implicit conf: L2CoherenceAgentConfiguration) extends XactTracker()(conf) { val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(4){ UInt() } - val state = RegReset(s_idle) + val state = Reg(init=s_idle) val xact = Reg{ new Release } - val init_client_id_ = RegReset(UInt(0, width = log2Up(ln.nClients))) - val release_data_needs_write = RegReset(Bool(false)) - val mem_cmd_sent = RegReset(Bool(false)) + val init_client_id_ = Reg(init=UInt(0, width = log2Up(ln.nClients))) + val release_data_needs_write = Reg(init=Bool(false)) + val mem_cmd_sent = Reg(init=Bool(false)) val cmd_to_write = Acquire(co.getUncachedWriteAcquireType, xact.addr, UInt(trackerId)) io.has_acquire_conflict := Bool(false) @@ -160,23 +160,23 @@ class VoluntaryReleaseTracker(trackerId: Int, bankId: Int)(implicit conf: L2Cohe class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: L2CoherenceAgentConfiguration) extends XactTracker()(conf) { val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UInt() } - val state = RegReset(s_idle) + val state = Reg(init=s_idle) val xact = Reg{ new Acquire } - val init_client_id_ = RegReset(UInt(0, width = log2Up(ln.nClients))) - val release_data_client_id = RegReset(UInt(0, width = log2Up(ln.nClients))) + val init_client_id_ = Reg(init=UInt(0, width = log2Up(ln.nClients))) + val release_data_client_id = Reg(init=UInt(0, width = log2Up(ln.nClients))) //TODO: Will need id reg for merged release xacts - val init_sharer_cnt_ = RegReset(UInt(0, width = log2Up(ln.nClients))) + val init_sharer_cnt_ = Reg(init=UInt(0, width = log2Up(ln.nClients))) val grant_type = co.getGrantType(xact.a_type, init_sharer_cnt_) - val release_count = if (ln.nClients == 1) UInt(0) else RegReset(UInt(0, width = log2Up(ln.nClients))) - val probe_flags = RegReset(Bits(0, width = ln.nClients)) + val release_count = if (ln.nClients == 1) UInt(0) else Reg(init=UInt(0, width = log2Up(ln.nClients))) + val probe_flags = Reg(init=Bits(0, width = ln.nClients)) val curr_p_id = PriorityEncoder(probe_flags) - val x_needs_read = RegReset(Bool(false)) - val acquire_data_needs_write = RegReset(Bool(false)) - val release_data_needs_write = RegReset(Bool(false)) + val x_needs_read = Reg(init=Bool(false)) + val acquire_data_needs_write = Reg(init=Bool(false)) + val release_data_needs_write = Reg(init=Bool(false)) val cmd_to_write = Acquire(co.getUncachedWriteAcquireType, xact.addr, UInt(trackerId)) val cmd_to_read = Acquire(co.getUncachedReadAcquireType, xact.addr, UInt(trackerId)) - val a_w_mem_cmd_sent = RegReset(Bool(false)) - val r_w_mem_cmd_sent = RegReset(Bool(false)) + val a_w_mem_cmd_sent = Reg(init=Bool(false)) + val r_w_mem_cmd_sent = Reg(init=Bool(false)) val probe_initial_flags = Bits(width = ln.nClients) probe_initial_flags := Bits(0) if (ln.nClients > 1) { @@ -296,7 +296,7 @@ class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: L2CoherenceAgen } abstract trait OuterRequestGenerator { - val mem_cnt = RegReset(UInt(0, width = log2Up(REFILL_CYCLES))) + val mem_cnt = Reg(init=UInt(0, width = log2Up(REFILL_CYCLES))) val mem_cnt_next = mem_cnt + UInt(1) def doOuterReqWrite[T <: HasTileLinkData](master_acq: PairedDataIO[LogicalNetworkIO[Acquire],LogicalNetworkIO[AcquireData]], client_data: DecoupledIO[LogicalNetworkIO[T]], cmd: Acquire, trigger: Bool, cmd_sent: Bool, desired_client_data_src_id: UInt) {