From 53987cd9d44f4e52af848000182c77cad318f5a2 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 8 Sep 2016 11:30:04 -0700 Subject: [PATCH 1/5] tilelink2 Nodes: support non-Bundle data for io type --- src/main/scala/uncore/tilelink2/LazyModule.scala | 2 +- src/main/scala/uncore/tilelink2/Nodes.scala | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/LazyModule.scala b/src/main/scala/uncore/tilelink2/LazyModule.scala index 8504e711..5937b363 100644 --- a/src/main/scala/uncore/tilelink2/LazyModule.scala +++ b/src/main/scala/uncore/tilelink2/LazyModule.scala @@ -16,7 +16,7 @@ abstract class LazyModule parent.foreach(p => p.children = this :: p.children) // Use as: connect(source -> sink, source2 -> sink2, ...) - def connect[PO, PI, EO, EI, B <: Bundle](edges: (BaseNode[PO, PI, EO, EI, B], BaseNode[PO, PI, EO, EI, B])*)(implicit sourceInfo: SourceInfo) = { + def connect[PO, PI, EO, EI, B <: Data](edges: (BaseNode[PO, PI, EO, EI, B], BaseNode[PO, PI, EO, EI, B])*)(implicit sourceInfo: SourceInfo) = { edges.foreach { case (source, sink) => bindings = (source edge sink) :: bindings } diff --git a/src/main/scala/uncore/tilelink2/Nodes.scala b/src/main/scala/uncore/tilelink2/Nodes.scala index 1679c17b..0dc8af9e 100644 --- a/src/main/scala/uncore/tilelink2/Nodes.scala +++ b/src/main/scala/uncore/tilelink2/Nodes.scala @@ -10,7 +10,7 @@ import chisel3.internal.sourceinfo.SourceInfo // PO = PortOutputParameters // EI = EdgeInput // EO = EdgeOutput -abstract class NodeImp[PO, PI, EO, EI, B <: Bundle] +abstract class NodeImp[PO, PI, EO, EI, B <: Data] { def edgeO(po: PO, pi: PI): EO def edgeI(po: PO, pi: PI): EI @@ -19,7 +19,7 @@ abstract class NodeImp[PO, PI, EO, EI, B <: Bundle] def connect(bo: B, eo: EO, bi: B, ei: EI)(implicit sourceInfo: SourceInfo): Unit } -class BaseNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])( +class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])( private val oFn: Option[Seq[PO] => PO], private val iFn: Option[Seq[PI] => PI], private val numPO: Range.Inclusive, @@ -72,34 +72,34 @@ class BaseNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])( } } -class IdentityNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B]) +class IdentityNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends BaseNode(imp)(Some{case Seq(x) => x}, Some{case Seq(x) => x}, 1 to 1, 1 to 1) -class OutputNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp) +class OutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp) { override def connectOut = bundleOut override def connectIn = bundleOut } -class InputNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp) +class InputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp) { override def connectOut = bundleIn override def connectIn = bundleIn } -class SourceNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1) +class SourceNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1) extends BaseNode(imp)(Some{case Seq() => po}, None, num, 0 to 0) { require (num.end >= 1) } -class SinkNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI, num: Range.Inclusive = 1 to 1) +class SinkNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI, num: Range.Inclusive = 1 to 1) extends BaseNode(imp)(None, Some{case Seq() => pi}, 0 to 0, num) { require (num.end >= 1) } -class InteriorNode[PO, PI, EO, EI, B <: Bundle](imp: NodeImp[PO, PI, EO, EI, B]) +class InteriorNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) (oFn: Seq[PO] => PO, iFn: Seq[PI] => PI, numPO: Range.Inclusive, numPI: Range.Inclusive) extends BaseNode(imp)(Some(oFn), Some(iFn), numPO, numPI) { From d7df7d3109f0bfd4c42020f915349f24ec3cfe4f Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 8 Sep 2016 14:41:08 -0700 Subject: [PATCH 2/5] tilelink2: connect Nodes to LazyModules for better error messages --- .../scala/uncore/tilelink2/LazyModule.scala | 11 +++++++++-- src/main/scala/uncore/tilelink2/Nodes.scala | 19 ++++++++++++++++--- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/LazyModule.scala b/src/main/scala/uncore/tilelink2/LazyModule.scala index 5937b363..92c6e0eb 100644 --- a/src/main/scala/uncore/tilelink2/LazyModule.scala +++ b/src/main/scala/uncore/tilelink2/LazyModule.scala @@ -3,12 +3,13 @@ package uncore.tilelink2 import Chisel._ -import chisel3.internal.sourceinfo._ +import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo} abstract class LazyModule { protected[tilelink2] var bindings = List[() => Unit]() protected[tilelink2] var children = List[LazyModule]() + protected[tilelink2] var nodes = List[RootNode]() protected[tilelink2] var info: SourceInfo = UnlocatableSourceInfo protected[tilelink2] val parent = LazyModule.stack.headOption @@ -22,6 +23,12 @@ abstract class LazyModule } } + def name = getClass.getName.split('.').last + def line = info match { + case SourceLine(filename, line, col) => s" ($filename:$line:$col)" + case _ => "" + } + def module: LazyModuleImp implicit val lazyModule = this @@ -55,6 +62,6 @@ abstract class LazyModuleImp(outer: LazyModule) extends Module // .module had better not be accessed while LazyModules are still being built! require (LazyModule.stack.isEmpty) - override def desiredName = outer.getClass.getName.split('.').last + override def desiredName = outer.name outer.instantiate() } diff --git a/src/main/scala/uncore/tilelink2/Nodes.scala b/src/main/scala/uncore/tilelink2/Nodes.scala index 0dc8af9e..a2231bbd 100644 --- a/src/main/scala/uncore/tilelink2/Nodes.scala +++ b/src/main/scala/uncore/tilelink2/Nodes.scala @@ -19,11 +19,20 @@ abstract class NodeImp[PO, PI, EO, EI, B <: Data] def connect(bo: B, eo: EO, bi: B, ei: EI)(implicit sourceInfo: SourceInfo): Unit } +class RootNode +{ + // You cannot create a Node outside a LazyModule! + require (!LazyModule.stack.isEmpty) + + val lazyModule = LazyModule.stack.head + lazyModule.nodes = this :: lazyModule.nodes +} + class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])( private val oFn: Option[Seq[PO] => PO], private val iFn: Option[Seq[PI] => PI], private val numPO: Range.Inclusive, - private val numPI: Range.Inclusive) + private val numPI: Range.Inclusive) extends RootNode { // At least 0 ports must be supported require (!numPO.isEmpty) @@ -42,8 +51,12 @@ class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])( private var oRealized = false private var iRealized = false - private lazy val oPorts = { oRealized = true; require (numPO.contains(accPO.size)); accPO.result() } - private lazy val iPorts = { iRealized = true; require (numPI.contains(accPI.size)); accPI.result() } + def name = lazyModule.name + "." + getClass.getName.split('.').last + private def reqO() = require(numPO.contains(accPO.size), s"${name} has ${accPO.size} outputs, expected ${numPO}${lazyModule.line}") + private def reqI() = require(numPI.contains(accPI.size), s"${name} has ${accPI.size} inputs, expected ${numPI}${lazyModule.line}") + + private lazy val oPorts = { oRealized = true; reqO(); accPO.result() } + private lazy val iPorts = { iRealized = true; reqI(); accPI.result() } private lazy val oParams : Option[PO] = oFn.map(_(iPorts.map(_.oParams.get))) private lazy val iParams : Option[PI] = iFn.map(_(oPorts.map(_.iParams.get))) From 23e896ed5dabef578c0c0155641095cfac56cb0a Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 8 Sep 2016 11:30:35 -0700 Subject: [PATCH 3/5] tilelink2 IntNodes: support interrupt graphs --- .../scala/uncore/tilelink2/IntNodes.scala | 72 +++++++++++++++++++ src/main/scala/uncore/tilelink2/package.scala | 1 + 2 files changed, 73 insertions(+) create mode 100644 src/main/scala/uncore/tilelink2/IntNodes.scala diff --git a/src/main/scala/uncore/tilelink2/IntNodes.scala b/src/main/scala/uncore/tilelink2/IntNodes.scala new file mode 100644 index 00000000..fb35a49f --- /dev/null +++ b/src/main/scala/uncore/tilelink2/IntNodes.scala @@ -0,0 +1,72 @@ +// See LICENSE for license details. + +package uncore.tilelink2 + +import Chisel._ +import scala.collection.mutable.ListBuffer +import scala.math.max +import chisel3.internal.sourceinfo.SourceInfo + +case class IntSourceParameters(device: String, num: Int) + +case class IntSinkPortParameters() +case class IntSourcePortParameters(sources: Seq[IntSourceParameters]) +{ + val num = sources.map(_.num).sum +} +case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters) + +object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]] +{ + def edgeO(po: IntSourcePortParameters, pi: IntSinkPortParameters): IntEdge = IntEdge(po, pi) + def edgeI(po: IntSourcePortParameters, pi: IntSinkPortParameters): IntEdge = IntEdge(po, pi) + def bundleO(eo: Seq[IntEdge]): Vec[Vec[Bool]] = { + if (eo.isEmpty) Vec(0, Vec(0, Bool())) else + Vec(eo.size, Vec(eo.map(_.source.num).max, Bool())) + } + def bundleI(ei: Seq[IntEdge]): Vec[Vec[Bool]] = { + require (!ei.isEmpty) + Vec(ei.size, Vec(ei.map(_.source.num).max, Bool())).flip + } + + def connect(bo: Vec[Bool], eo: IntEdge, bi: Vec[Bool], ei: IntEdge)(implicit sourceInfo: SourceInfo): Unit = { + require (eo == ei) + // Cannot use bulk connect, because the widths could differ + (bo zip bi) foreach { case (o, i) => i := o } + } +} + +case class IntIdentityNode() extends IdentityNode(IntImp) +case class IntOutputNode() extends OutputNode(IntImp) +case class IntInputNode() extends InputNode(IntImp) + +case class IntSourceNode(device: String, num: Int) extends SourceNode(IntImp)( + IntSourcePortParameters(Seq(IntSourceParameters(device, num))), + (if (num == 0) 0 else 1) to 1) +case class IntSinkNode() extends SinkNode(IntImp)(IntSinkPortParameters()) + +case class IntAdapterNode( + sourceFn: Seq[IntSourcePortParameters] => IntSourcePortParameters, + sinkFn: Seq[IntSinkPortParameters] => IntSinkPortParameters, + numSourcePorts: Range.Inclusive = 1 to 1, + numSinkPorts: Range.Inclusive = 1 to 1) + extends InteriorNode(IntImp)(sourceFn, sinkFn, numSourcePorts, numSinkPorts) + +class IntXbar extends LazyModule +{ + val intnode = IntAdapterNode( + numSourcePorts = 1 to 1, // does it make sense to have more than one interrupt sink? + numSinkPorts = 1 to 128, + sourceFn = { seq => IntSourcePortParameters(seq.map(_.sources).flatten) }, + sinkFn = { _ => IntSinkPortParameters() }) + + lazy val module = new LazyModuleImp(this) { + val io = new Bundle { + val in = intnode.bundleIn + val out = intnode.bundleOut + } + + val cat = (intnode.edgesIn zip io.in).map{ case (e, i) => i.take(e.source.num) }.flatten + io.out.foreach { _ := cat } + } +} diff --git a/src/main/scala/uncore/tilelink2/package.scala b/src/main/scala/uncore/tilelink2/package.scala index b1e3dda2..cb78a633 100644 --- a/src/main/scala/uncore/tilelink2/package.scala +++ b/src/main/scala/uncore/tilelink2/package.scala @@ -5,6 +5,7 @@ import Chisel._ package object tilelink2 { type TLBaseNode = BaseNode[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle] + type IntBaseNode = BaseNode[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]] def OH1ToUInt(x: UInt) = OHToUInt((x << 1 | UInt(1)) ^ x) def UIntToOH1(x: UInt, width: Int) = ~(SInt(-1, width=width).asUInt << x)(width-1, 0) def trailingZeros(x: Int) = if (x > 0) Some(log2Ceil(x & -x)) else None From 66f58cf2d0f646576069ad5e380029937a0447d4 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 8 Sep 2016 15:17:30 -0700 Subject: [PATCH 4/5] tilelink2 RegisterRouter: support new TL2 interrupts --- src/main/scala/uncore/tilelink2/GPIO.scala | 14 +++++++--- .../scala/uncore/tilelink2/RegField.scala | 1 + .../uncore/tilelink2/RegisterRouter.scala | 26 +++++++++++++------ 3 files changed, 30 insertions(+), 11 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/GPIO.scala b/src/main/scala/uncore/tilelink2/GPIO.scala index a9050882..6b4e1e4b 100644 --- a/src/main/scala/uncore/tilelink2/GPIO.scala +++ b/src/main/scala/uncore/tilelink2/GPIO.scala @@ -16,14 +16,22 @@ trait GPIOModule extends HasRegMap { val params: GPIOParams val io: GPIOBundle + val interrupts: Vec[Bool] val state = RegInit(UInt(0)) - io.gpio := state + val pending = RegInit(UInt(0xf, width = 4)) - regmap(0 -> Seq(RegField(params.num, state))) + io.gpio := state + interrupts := pending.toBools + + regmap( + 0 -> Seq( + RegField(params.num, state)), + 1 -> Seq( + RegField.w1ToClear(4, pending, state))) } // Create a concrete TL2 version of the abstract GPIO slave -class TLGPIO(p: GPIOParams) extends TLRegisterRouter(p.address)( +class TLGPIO(p: GPIOParams) extends TLRegisterRouter(p.address, 4)( new TLRegBundle(p, _) with GPIOBundle)( new TLRegModule(p, _, _) with GPIOModule) diff --git a/src/main/scala/uncore/tilelink2/RegField.scala b/src/main/scala/uncore/tilelink2/RegField.scala index 32a65c0d..9c324534 100644 --- a/src/main/scala/uncore/tilelink2/RegField.scala +++ b/src/main/scala/uncore/tilelink2/RegField.scala @@ -86,6 +86,7 @@ object RegField trait HasRegMap { def regmap(mapping: RegField.Map*): Unit + val interrupts: Vec[Bool] } // See GPIO.scala for an example of how to use regmap diff --git a/src/main/scala/uncore/tilelink2/RegisterRouter.scala b/src/main/scala/uncore/tilelink2/RegisterRouter.scala index e455efda..a3b61da7 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouter.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouter.scala @@ -75,29 +75,39 @@ object TLRegisterNode // register mapped device from a totally abstract register mapped device. // See GPIO.scala in this directory for an example -abstract class TLRegisterRouterBase(address: AddressSet, concurrency: Option[Int], beatBytes: Int) extends LazyModule +abstract class TLRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Option[Int], beatBytes: Int) extends LazyModule { val node = TLRegisterNode(address, concurrency, beatBytes) + val intnode = IntSourceNode(name + s" @ ${address.base}", interrupts) } -class TLRegBundle[P](val params: P, val in: Vec[TLBundle]) extends Bundle +case class TLRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[TLBundle]) -class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase) +class TLRegBundleBase(arg: TLRegBundleArg) extends Bundle +{ + val interrupts = arg.interrupts + val in = arg.in +} + +class TLRegBundle[P](val params: P, arg: TLRegBundleArg) extends TLRegBundleBase(arg) + +class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase) extends LazyModuleImp(router) with HasRegMap { val io = bundleBuilder + val interrupts = if (io.interrupts.isEmpty) Vec(0, Bool()) else io.interrupts(0) def regmap(mapping: RegField.Map*) = router.node.regmap(mapping:_*) } -class TLRegisterRouter[B <: Bundle, M <: LazyModuleImp] - (base: BigInt, size: BigInt = 4096, concurrency: Option[Int] = None, beatBytes: Int = 4) - (bundleBuilder: Vec[TLBundle] => B) +class TLRegisterRouter[B <: TLRegBundleBase, M <: LazyModuleImp] + (base: BigInt, interrupts: Int = 0, size: BigInt = 4096, concurrency: Option[Int] = None, beatBytes: Int = 4) + (bundleBuilder: TLRegBundleArg => B) (moduleBuilder: (=> B, TLRegisterRouterBase) => M) - extends TLRegisterRouterBase(AddressSet(base, size-1), concurrency, beatBytes) + extends TLRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes) { require (size % 4096 == 0) // devices should be 4K aligned require (isPow2(size)) require (size >= 4096) - lazy val module = moduleBuilder(bundleBuilder(node.bundleIn), this) + lazy val module = moduleBuilder(bundleBuilder(TLRegBundleArg(intnode.bundleOut, node.bundleIn)), this) } From 1b07d53f70c506f6607fe021f7b12beb85a53fdb Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 8 Sep 2016 18:51:43 -0700 Subject: [PATCH 5/5] tilelink2 IntNodes: record interrupt ranges in parameters --- .../scala/uncore/tilelink2/IntNodes.scala | 30 ++++++++++++++++--- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/IntNodes.scala b/src/main/scala/uncore/tilelink2/IntNodes.scala index fb35a49f..df3e6152 100644 --- a/src/main/scala/uncore/tilelink2/IntNodes.scala +++ b/src/main/scala/uncore/tilelink2/IntNodes.scala @@ -7,12 +7,30 @@ import scala.collection.mutable.ListBuffer import scala.math.max import chisel3.internal.sourceinfo.SourceInfo -case class IntSourceParameters(device: String, num: Int) +// A potentially empty half-open range; [start, end) +case class IntRange(start: Int, end: Int) +{ + require (start >= 0) + require (start <= end) + def size = end - start + def overlaps(x: IntRange) = start < x.end && x.start < end + def offset(x: Int) = IntRange(x+start, x+end) +} +object IntRange +{ + implicit def apply(end: Int): IntRange = apply(0, end) +} + +case class IntSourceParameters(device: String, range: IntRange) case class IntSinkPortParameters() case class IntSourcePortParameters(sources: Seq[IntSourceParameters]) { - val num = sources.map(_.num).sum + val num = sources.map(_.range.size).sum + // The interrupts mapping must not overlap + sources.map(_.range).combinations(2).foreach { case Seq(a, b) => require (!a.overlaps(b)) } + // The interrupts must perfectly cover the range + require (sources.map(_.range.end).max == num) } case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters) @@ -57,8 +75,12 @@ class IntXbar extends LazyModule val intnode = IntAdapterNode( numSourcePorts = 1 to 1, // does it make sense to have more than one interrupt sink? numSinkPorts = 1 to 128, - sourceFn = { seq => IntSourcePortParameters(seq.map(_.sources).flatten) }, - sinkFn = { _ => IntSinkPortParameters() }) + sinkFn = { _ => IntSinkPortParameters() }, + sourceFn = { seq => + IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map { + case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o))) + }.flatten) + }) lazy val module = new LazyModuleImp(this) { val io = new Bundle {