riscv/rocket-chip
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Don't use Vec as lvalue

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This commit is contained in:
Andrew Waterman
2015-08-05 15:29:33 -07:00
parent 546205b174
commit 1718333f83
1 changed files with 4 additions and 2 deletions
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6
rocket/src/main/scala/fpu.scala
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@@ -131,8 +131,10 @@ class FPUDecoder extends Module
FSQRT_D -> List(FCMD_SQRT, N,Y,Y,N,N,Y,X,N,N,N,N,N,N,Y,Y,Y)
))
val s = io.sigs
Vec(s.cmd, s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12, s.swap23, s.single, s.fromint,
s.toint, s.fastpipe, s.fma, s.div, s.sqrt, s.round, s.wflags) := decoder
val sigs = Seq(s.cmd, s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.single, s.fromint, s.toint, s.fastpipe, s.fma,
s.div, s.sqrt, s.round, s.wflags)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUIO extends Bundle {