riscv/rocket-chip
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SystemBus: remove misnamed functions (#972)

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These functions were actually for cross connecting chips.
This commit is contained in:
Wesley W. Terpstra 2017-08-24 23:35:01 +02:00 committed by GitHub
parent 6e689f55ed
commit 17134125e1
1 changed files with 1 additions and 13 deletions
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14
src/main/scala/coreplex/SystemBus.scala
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@ -29,10 +29,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable)) private val tile_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all)) private val port_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
private val master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
master_splitter.node :=* tile_fixer.node master_splitter.node :=* tile_fixer.node
master_splitter.node :=* port_fixer.node master_splitter.node :=* port_fixer.node
inwardNode :=* master_fixer.node
def toSplitSlaves: TLOutwardNode = outwardSplitNode def toSplitSlaves: TLOutwardNode = outwardSplitNode
@ -42,17 +40,7 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
val toSlave: TLOutwardNode = outwardBufNode val toSlave: TLOutwardNode = outwardBufNode
def fromAsyncMasters(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = { def fromCoherentChip: TLInwardNode = inwardNode
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
master_fixer.node :=* sink.node
sink.node
}
def fromSyncMasters(params: BufferParams = BufferParams.default): TLInwardNode = {
val buffer = LazyModule(new TLBuffer(params))
master_fixer.node :=* buffer.node
buffer.node
}
def fromSyncTiles(params: BufferParams): TLInwardNode = { def fromSyncTiles(params: BufferParams): TLInwardNode = {
val buf = LazyModule(new TLBuffer(params)) val buf = LazyModule(new TLBuffer(params))