Refactor the TransactionTracker logic in all the L2 TileLink Managers.
They now share common sub-transactions within traits, and use a common set of state transitions and scoreboarding logic. Tracker allocation logic has also been updated. No changes to external IOs or the TileLink protocol. A new bufferless Broadcast hub is also included, but does not yet pass fuzzing checks.
This commit is contained in:
Henry Cook
Howard Mao
@ -4,390 +4,198 @@ package uncore
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import Chisel._
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import cde.{Parameters, Field}
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case object L2StoreDataQueueDepth extends Field[Int]
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class L2BroadcastHub(implicit p: Parameters) extends HierarchicalCoherenceAgent()(p) {
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trait HasBroadcastHubParameters extends HasCoherenceAgentParameters {
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val sdqDepth = p(L2StoreDataQueueDepth)*innerDataBeats
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val dqIdxBits = math.max(log2Up(nReleaseTransactors) + 1, log2Up(sdqDepth))
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val nDataQueueLocations = 3 //Stores, VoluntaryWBs, Releases
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}
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class DataQueueLocation(implicit p: Parameters) extends CoherenceAgentBundle()(p)
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with HasBroadcastHubParameters {
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val idx = UInt(width = dqIdxBits)
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val loc = UInt(width = log2Ceil(nDataQueueLocations))
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}
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object DataQueueLocation {
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def apply(idx: UInt, loc: UInt)(implicit p: Parameters) = {
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val d = Wire(new DataQueueLocation)
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d.idx := idx
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d.loc := loc
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d
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}
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}
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class L2BroadcastHub(implicit p: Parameters) extends ManagerCoherenceAgent()(p)
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with HasBroadcastHubParameters {
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val internalDataBits = new DataQueueLocation().getWidth
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val inStoreQueue :: inVolWBQueue :: inClientReleaseQueue :: Nil = Enum(UInt(), nDataQueueLocations)
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val usingStoreDataQueue = p.alterPartial({
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case TLKey(`innerTLId`) => innerTLParams.copy(overrideDataBitsPerBeat = Some(internalDataBits))
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case TLKey(`outerTLId`) => outerTLParams.copy(overrideDataBitsPerBeat = Some(internalDataBits))
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})
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// Create SHRs for outstanding transactions
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val trackerList =
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// Create TSHRs for outstanding transactions
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val irelTrackerList =
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(0 until nReleaseTransactors).map(id =>
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Module(new BroadcastVoluntaryReleaseTracker(id)(usingStoreDataQueue))) ++
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Module(new BufferedBroadcastVoluntaryReleaseTracker(id)))
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val iacqTrackerList =
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(nReleaseTransactors until nTransactors).map(id =>
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Module(new BroadcastAcquireTracker(id)(usingStoreDataQueue)))
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Module(new BufferedBroadcastAcquireTracker(id)))
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val trackerList = irelTrackerList ++ iacqTrackerList
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// Propagate incoherence flags
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trackerList.map(_.io.incoherent := io.incoherent)
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trackerList.map(_.io.incoherent) foreach { _ := io.incoherent }
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// Queue to store impending Put data
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val sdq = Reg(Vec(sdqDepth, io.iacq().data))
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val sdq_val = Reg(init=Bits(0, sdqDepth))
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val sdq_alloc_id = PriorityEncoder(~sdq_val)
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val sdq_rdy = !sdq_val.andR
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val sdq_enq = trackerList.map( t =>
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(t.io.alloc.iacq || t.io.matches.iacq) &&
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t.io.inner.acquire.fire() &&
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t.io.iacq().hasData()
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).reduce(_||_)
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when (sdq_enq) { sdq(sdq_alloc_id) := io.iacq().data }
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// Create an arbiter for the one memory port
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val outerList = trackerList.map(_.io.outer)
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val outer_arb = Module(new ClientTileLinkIOArbiter(outerList.size)
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(p.alterPartial({ case TLId => p(OuterTLId) })))
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outer_arb.io.in <> outerList
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io.outer <> outer_arb.io.out
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// Handle acquire transaction initiation
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val irel_vs_iacq_conflict =
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io.inner.acquire.valid &&
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io.inner.release.valid &&
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io.irel().conflicts(io.iacq())
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val sdqLoc = List.fill(nTransactors) {
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DataQueueLocation(sdq_alloc_id, inStoreQueue).toBits
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}
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doInputRoutingWithAllocation(
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io.inner.acquire,
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trackerList.map(_.io.inner.acquire),
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trackerList.map(_.io.matches.iacq),
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trackerList.map(_.io.alloc.iacq),
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Some(sdqLoc),
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Some(sdq_rdy && !irel_vs_iacq_conflict),
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Some(sdq_rdy))
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io.inner.acquire.valid &&
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io.inner.release.valid &&
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io.irel().conflicts(io.iacq())
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// Queue to store impending Voluntary Release data
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val voluntary = io.irel().isVoluntary()
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val vwbdq_enq = io.inner.release.fire() && voluntary && io.irel().hasData()
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val (rel_data_cnt, rel_data_done) = Counter(vwbdq_enq, innerDataBeats) //TODO Zero width
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val vwbdq = Reg(Vec(innerDataBeats, io.irel().data)) //TODO Assumes nReleaseTransactors == 1
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when(vwbdq_enq) { vwbdq(rel_data_cnt) := io.irel().data }
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doInputRoutingWithAllocation(
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in = io.inner.acquire,
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outs = trackerList.map(_.io.inner.acquire),
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allocs = trackerList.map(_.io.alloc_iacq),
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allocOverride = !irel_vs_iacq_conflict)
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// Handle releases, which might be voluntary and might have data
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val vwbqLoc = (0 until nTransactors).map(i =>
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(DataQueueLocation(rel_data_cnt,
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(if(i < nReleaseTransactors) inVolWBQueue
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else inClientReleaseQueue)).toBits))
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doInputRoutingWithAllocation(
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io.inner.release,
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trackerList.map(_.io.inner.release),
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trackerList.map(_.io.matches.irel),
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trackerList.map(_.io.alloc.irel),
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Some(vwbqLoc))
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in = io.inner.release,
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outs = trackerList.map(_.io.inner.release),
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allocs = trackerList.map(_.io.alloc_irel))
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// Wire probe requests and grant reply to clients, finish acks from clients
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// Note that we bypass the Grant data subbundles
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doOutputArbitration(io.inner.grant, trackerList.map(_.io.inner.grant))
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io.inner.grant.bits.data := io.outer.grant.bits.data
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io.inner.grant.bits.addr_beat := io.outer.grant.bits.addr_beat
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doOutputArbitration(io.inner.probe, trackerList.map(_.io.inner.probe))
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doOutputArbitration(io.inner.grant, trackerList.map(_.io.inner.grant))
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doInputRouting(io.inner.finish, trackerList.map(_.io.inner.finish))
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// Create an arbiter for the one memory port
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val outer_arb = Module(new ClientUncachedTileLinkIOArbiter(trackerList.size)
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(usingStoreDataQueue.alterPartial({ case TLId => p(OuterTLId) })))
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outer_arb.io.in <> trackerList.map(_.io.outer)
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// Get the pending data out of the store data queue
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val outer_data_ptr = new DataQueueLocation().fromBits(outer_arb.io.out.acquire.bits.data)
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val is_in_sdq = outer_data_ptr.loc === inStoreQueue
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val free_sdq = io.outer.acquire.fire() &&
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io.outer.acquire.bits.hasData() &&
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outer_data_ptr.loc === inStoreQueue
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io.outer <> outer_arb.io.out
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io.outer.acquire.bits.data := MuxLookup(outer_data_ptr.loc, io.irel().data, Array(
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inStoreQueue -> sdq(outer_data_ptr.idx),
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inVolWBQueue -> vwbdq(outer_data_ptr.idx)))
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// Update SDQ valid bits
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when (io.outer.acquire.valid || sdq_enq) {
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sdq_val := sdq_val & ~(UIntToOH(outer_data_ptr.idx) & Fill(sdqDepth, free_sdq)) |
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PriorityEncoderOH(~sdq_val(sdqDepth-1,0)) & Fill(sdqDepth, sdq_enq)
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}
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}
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class BroadcastXactTracker(implicit p: Parameters) extends XactTracker()(p) {
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val io = new ManagerXactTrackerIO
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val io = new HierarchicalXactTrackerIO
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pinAllReadyValidLow(io)
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}
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class BroadcastVoluntaryReleaseTracker(trackerId: Int)
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(implicit p: Parameters) extends BroadcastXactTracker()(p) {
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val s_idle :: s_busy :: Nil = Enum(UInt(), 2)
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val state = Reg(init=s_idle)
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trait BroadcastsToAllClients extends HasCoherenceAgentParameters {
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val coh = HierarchicalMetadata.onReset
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val inner_coh = coh.inner
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val outer_coh = coh.outer
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def full_representation = ~UInt(0, width = innerNCachingClients)
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}
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val xact = Reg(new BufferedReleaseFromSrc()(p.alterPartial({ case TLId => innerTLId })))
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val coh = ManagerMetadata.onReset
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val pending_irels = Reg(init=Bits(0, width = io.inner.tlDataBeats))
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val pending_writes = Reg(init=Bits(0, width = io.outer.tlDataBeats))
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val pending_ignt = Reg(init=Bool(false))
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val all_pending_done = !(pending_irels.orR || pending_writes.orR || pending_ignt)
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// Accept a voluntary Release (and any further beats of data)
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pending_irels := (pending_irels & dropPendingBitWhenBeatHasData(io.inner.release))
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io.inner.release.ready := ((state === s_idle) && io.irel().isVoluntary()) || pending_irels.orR
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when(io.inner.release.fire()) { xact.data_buffer(io.irel().addr_beat) := io.irel().data }
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// Write the voluntarily written back data to outer memory using an Acquire.PutBlock
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//TODO: Use io.outer.release instead?
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pending_writes := (pending_writes & dropPendingBitWhenBeatHasData(io.outer.acquire)) |
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addPendingBitWhenBeatHasData(io.inner.release)
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val curr_write_beat = PriorityEncoder(pending_writes)
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io.outer.acquire.valid := state === s_busy && pending_writes.orR
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io.outer.acquire.bits := PutBlock(
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client_xact_id = UInt(trackerId),
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addr_block = xact.addr_block,
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addr_beat = curr_write_beat,
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data = xact.data_buffer(curr_write_beat))
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(p.alterPartial({ case TLId => outerTLId }))
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// Send an acknowledgement
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io.inner.grant.valid := state === s_busy && pending_ignt && !pending_irels && io.outer.grant.valid
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io.inner.grant.bits := coh.makeGrant(xact)
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when(io.inner.grant.fire()) { pending_ignt := Bool(false) }
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io.outer.grant.ready := state === s_busy && io.inner.grant.ready
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// State machine updates and transaction handler metadata intialization
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when(state === s_idle && io.inner.release.valid && io.alloc.irel) {
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xact := io.irel()
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when(io.irel().hasMultibeatData()) {
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pending_irels := dropPendingBitWhenBeatHasData(io.inner.release)
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}. otherwise {
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pending_irels := UInt(0)
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}
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pending_writes := addPendingBitWhenBeatHasData(io.inner.release)
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pending_ignt := io.irel().requiresAck()
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state := s_busy
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}
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when(state === s_busy && all_pending_done) { state := s_idle }
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// These IOs are used for routing in the parent
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io.matches.iacq := (state =/= s_idle) && xact.conflicts(io.iacq())
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io.matches.irel := (state =/= s_idle) && xact.conflicts(io.irel()) && io.irel().isVoluntary()
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io.matches.oprb := Bool(false)
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abstract class BroadcastVoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters)
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extends VoluntaryReleaseTracker(trackerId)(p)
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with EmitsVoluntaryReleases
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with BroadcastsToAllClients {
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val io = new HierarchicalXactTrackerIO
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pinAllReadyValidLow(io)
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// Checks for illegal behavior
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assert(!(state === s_idle && io.inner.release.fire() && !io.irel().isVoluntary()),
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assert(!(state === s_idle && io.inner.release.fire() && io.alloc_irel.should && !io.irel().isVoluntary()),
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"VoluntaryReleaseTracker accepted Release that wasn't voluntary!")
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}
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class BroadcastAcquireTracker(trackerId: Int)
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(implicit p: Parameters) extends BroadcastXactTracker()(p) {
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val s_idle :: s_probe :: s_mem_read :: s_mem_write :: s_make_grant :: s_mem_resp :: s_ack :: Nil = Enum(UInt(), 7)
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val state = Reg(init=s_idle)
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abstract class BroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters)
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extends AcquireTracker(trackerId)(p)
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with EmitsVoluntaryReleases
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with BroadcastsToAllClients {
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val io = new HierarchicalXactTrackerIO
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pinAllReadyValidLow(io)
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val xact = Reg(new BufferedAcquireFromSrc()(p.alterPartial({ case TLId => innerTLId })))
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val coh = ManagerMetadata.onReset
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val alwaysWriteFullBeat = false
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val nSecondaryMisses = 1
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def iacq_can_merge = Bool(false)
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assert(!(state =/= s_idle && xact.isBuiltInType() &&
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Vec(Acquire.putAtomicType, Acquire.getPrefetchType, Acquire.putPrefetchType).contains(xact.a_type)),
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"Broadcast Hub does not support PutAtomics or prefetches") // TODO
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val release_count = Reg(init=UInt(0, width = log2Up(io.inner.tlNCachingClients+1)))
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val pending_probes = Reg(init=Bits(0, width = io.inner.tlNCachingClients))
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val curr_p_id = PriorityEncoder(pending_probes)
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val mask_self = SInt(-1, width = io.inner.tlNCachingClients)
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.toUInt
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.bitSet(io.inner.acquire.bits.client_id, io.inner.acquire.bits.requiresSelfProbe())
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val mask_incoherent = mask_self & ~io.incoherent.toBits
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val collect_iacq_data = Reg(init=Bool(false))
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val iacq_data_valid = Reg(init=Bits(0, width = innerDataBeats))
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val iacq_data_done = connectIncomingDataBeatCounter(io.inner.acquire)
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val irel_data_done = connectIncomingDataBeatCounter(io.inner.release)
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val (ignt_data_cnt, ignt_data_done) = connectOutgoingDataBeatCounter(io.inner.grant)
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val (oacq_data_cnt, oacq_data_done) = connectOutgoingDataBeatCounter(io.outer.acquire)
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val ognt_data_done = connectIncomingDataBeatCounter(io.outer.grant)
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val pending_ognt_ack = Reg(init=Bool(false))
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val pending_outer_write = xact.hasData()
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val pending_outer_write_ = io.iacq().hasData()
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val pending_outer_read = io.ignt().hasData()
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val pending_outer_read_ = coh.makeGrant(io.iacq(), UInt(trackerId)).hasData()
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val subblock_type = xact.isSubBlockType()
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// These IOs are used for routing in the parent
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io.matches.iacq := (state =/= s_idle) && xact.conflicts(io.iacq())
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io.matches.irel := (state =/= s_idle) && xact.conflicts(io.irel()) && !io.irel().isVoluntary()
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io.matches.oprb := Bool(false)
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val outerParams = p.alterPartial({ case TLId => outerTLId })
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val oacq_probe = PutBlock(
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client_xact_id = UInt(trackerId),
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addr_block = io.irel().addr_block,
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addr_beat = io.irel().addr_beat,
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data = io.irel().data)(outerParams)
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val oacq_write_beat = Put(
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client_xact_id = UInt(trackerId),
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addr_block = xact.addr_block,
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addr_beat = xact.addr_beat,
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data = xact.data_buffer(0),
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wmask = xact.wmask())(outerParams)
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val oacq_write_block = PutBlock(
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client_xact_id = UInt(trackerId),
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addr_block = xact.addr_block,
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addr_beat = oacq_data_cnt,
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data = xact.data_buffer(oacq_data_cnt),
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wmask = xact.wmask_buffer(oacq_data_cnt))(outerParams)
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val oacq_read_beat = Get(
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client_xact_id = UInt(trackerId),
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addr_block = xact.addr_block,
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addr_beat = xact.addr_beat,
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addr_byte = xact.addr_byte(),
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operand_size = xact.op_size(),
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alloc = Bool(false))(outerParams)
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val oacq_read_block = GetBlock(
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client_xact_id = UInt(trackerId),
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addr_block = xact.addr_block)(outerParams)
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io.outer.acquire.valid := Bool(false)
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io.outer.acquire.bits := Mux(state === s_probe, oacq_probe,
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Mux(state === s_mem_write,
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Mux(subblock_type, oacq_write_beat, oacq_write_block),
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Mux(subblock_type, oacq_read_beat, oacq_read_block)))
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io.outer.grant.ready := Bool(false)
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io.inner.probe.valid := Bool(false)
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io.inner.probe.bits := coh.makeProbe(curr_p_id, xact)
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io.inner.grant.valid := Bool(false)
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io.inner.grant.bits := coh.makeGrant(xact, UInt(trackerId)) // Data bypassed in parent
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io.inner.acquire.ready := Bool(false)
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io.inner.release.ready := Bool(false)
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io.inner.finish.ready := Bool(false)
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assert(!(state =/= s_idle && collect_iacq_data && io.inner.acquire.fire() &&
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io.iacq().client_id =/= xact.client_id),
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"AcquireTracker accepted data beat from different network source than initial request.")
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assert(!(state =/= s_idle && collect_iacq_data && io.inner.acquire.fire() &&
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io.iacq().client_xact_id =/= xact.client_xact_id),
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"AcquireTracker accepted data beat from different client transaction than initial request.")
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assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc.iacq &&
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io.iacq().hasMultibeatData() && io.iacq().addr_beat =/= UInt(0)),
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// Checks for illegal behavior
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// TODO: this could be allowed, but is a useful check against allocation gone wild
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assert(!(state === s_idle && io.inner.acquire.fire() && io.alloc_iacq.should &&
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io.iacq().hasMultibeatData() && !io.iacq().first()),
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"AcquireTracker initialized with a tail data beat.")
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when(collect_iacq_data) {
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io.inner.acquire.ready := Bool(true)
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when(io.inner.acquire.valid) {
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xact.data_buffer(io.iacq().addr_beat) := io.iacq().data
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xact.wmask_buffer(io.iacq().addr_beat) := io.iacq().wmask()
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iacq_data_valid := iacq_data_valid.bitSet(io.iacq().addr_beat, Bool(true))
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}
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when(iacq_data_done) { collect_iacq_data := Bool(false) }
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}
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assert(!(state =/= s_idle && pending_ignt && xact_iacq.isPrefetch()),
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"Broadcast Hub does not support Prefetches.")
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assert(!(state =/= s_idle && pending_ignt && xact_iacq.isAtomic()),
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"Broadcast Hub does not support PutAtomics.")
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}
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class BufferedBroadcastVoluntaryReleaseTracker(trackerId: Int)(implicit p: Parameters)
|
||||
extends BroadcastVoluntaryReleaseTracker(trackerId)(p)
|
||||
with HasDataBuffer {
|
||||
|
||||
// Tell the parent if any incoming messages conflict with the ongoing transaction
|
||||
routeInParent()
|
||||
io.alloc_iacq.can := Bool(false)
|
||||
|
||||
// Start transaction by accepting inner release
|
||||
innerRelease(block_vol_ignt = pending_orel || vol_ognt_counter.pending)
|
||||
|
||||
// A release beat can be accepted if we are idle, if its a mergeable transaction, or if its a tail beat
|
||||
io.inner.release.ready := state === s_idle || irel_can_merge || irel_same_xact
|
||||
|
||||
when(irel_is_allocating) { pending_orel := io.irel().hasData() }
|
||||
|
||||
when(io.inner.release.fire()) { data_buffer(io.irel().addr_beat) := io.irel().data }
|
||||
|
||||
// Dispatch outer release
|
||||
outerRelease(
|
||||
coh = outer_coh.onHit(M_XWR),
|
||||
data = data_buffer(vol_ognt_counter.up.idx))
|
||||
|
||||
quiesce()
|
||||
}
|
||||
|
||||
class BufferedBroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters)
|
||||
extends BroadcastAcquireTracker(trackerId)(p)
|
||||
with HasByteWriteMaskBuffer {
|
||||
|
||||
// Setup IOs used for routing in the parent
|
||||
routeInParent()
|
||||
io.alloc_irel.can := Bool(false)
|
||||
|
||||
// First, take care of accpeting new acquires or secondary misses
|
||||
// Handling of primary and secondary misses' data and write mask merging
|
||||
innerAcquire(
|
||||
can_alloc = Bool(false),
|
||||
next = s_inner_probe)
|
||||
|
||||
io.inner.acquire.ready := state === s_idle || iacq_can_merge || iacq_same_xact
|
||||
|
||||
// Track which clients yet need to be probed and make Probe message
|
||||
// If a writeback occurs, we can forward its data via the buffer,
|
||||
// and skip having to go outwards
|
||||
val skip_outer_acquire = pending_ignt_data.andR
|
||||
|
||||
innerProbe(
|
||||
inner_coh.makeProbe(curr_probe_dst, xact_iacq, xact_addr_block),
|
||||
Mux(!skip_outer_acquire, s_outer_acquire, s_busy))
|
||||
|
||||
// Handle incoming releases from clients, which may reduce sharer counts
|
||||
// and/or write back dirty data, and may be unexpected voluntary releases
|
||||
def irel_can_merge = io.irel().conflicts(xact_addr_block) &&
|
||||
io.irel().isVoluntary() &&
|
||||
!Vec(s_idle, s_meta_write).contains(state) &&
|
||||
!all_pending_done &&
|
||||
!io.outer.grant.fire() &&
|
||||
!io.inner.grant.fire() &&
|
||||
!vol_ignt_counter.pending
|
||||
|
||||
innerRelease(block_vol_ignt = vol_ognt_counter.pending)
|
||||
|
||||
//TODO: accept vol irels when state === s_idle, operate like the VolRelTracker
|
||||
io.inner.release.ready := irel_can_merge || irel_same_xact
|
||||
|
||||
mergeDataInner(io.inner.release)
|
||||
|
||||
// If there was a writeback, forward it outwards
|
||||
outerRelease(
|
||||
coh = outer_coh.onHit(M_XWR),
|
||||
data = data_buffer(vol_ognt_counter.up.idx))
|
||||
|
||||
// Send outer request for miss
|
||||
outerAcquire(
|
||||
caching = !xact_iacq.isBuiltInType(),
|
||||
coh = outer_coh,
|
||||
data = data_buffer(ognt_counter.up.idx),
|
||||
wmask = wmask_buffer(ognt_counter.up.idx),
|
||||
next = s_busy)
|
||||
|
||||
// Handle the response from outer memory
|
||||
mergeDataOuter(io.outer.grant)
|
||||
|
||||
// Acknowledge or respond with data
|
||||
innerGrant(
|
||||
data = data_buffer(ignt_data_idx),
|
||||
external_pending = pending_orel || ognt_counter.pending || vol_ognt_counter.pending)
|
||||
|
||||
when(iacq_is_allocating) {
|
||||
wmask_buffer.foreach { w => w := UInt(0) } // This is the only reg that must be clear in s_idle
|
||||
initializeProbes()
|
||||
}
|
||||
|
||||
initDataInner(io.inner.acquire)
|
||||
|
||||
// Wait for everything to quiesce
|
||||
quiesce()
|
||||
|
||||
when(pending_ognt_ack) {
|
||||
io.outer.grant.ready := Bool(true)
|
||||
when(io.outer.grant.valid) { pending_ognt_ack := Bool(false) }
|
||||
//TODO add finish queue if this isnt the last level manager
|
||||
}
|
||||
|
||||
switch (state) {
|
||||
is(s_idle) {
|
||||
io.inner.acquire.ready := Bool(true)
|
||||
when(io.inner.acquire.valid && io.alloc.iacq) {
|
||||
xact := io.iacq()
|
||||
xact.data_buffer(UInt(0)) := io.iacq().data
|
||||
xact.wmask_buffer(UInt(0)) := io.iacq().wmask()
|
||||
collect_iacq_data := io.iacq().hasMultibeatData()
|
||||
iacq_data_valid := io.iacq().hasData() << io.iacq().addr_beat
|
||||
val needs_probes = mask_incoherent.orR
|
||||
when(needs_probes) {
|
||||
pending_probes := mask_incoherent
|
||||
release_count := PopCount(mask_incoherent)
|
||||
}
|
||||
state := Mux(needs_probes, s_probe,
|
||||
Mux(pending_outer_write_, s_mem_write,
|
||||
Mux(pending_outer_read_, s_mem_read, s_make_grant)))
|
||||
}
|
||||
}
|
||||
is(s_probe) {
|
||||
// Generate probes
|
||||
io.inner.probe.valid := pending_probes.orR
|
||||
when(io.inner.probe.ready) {
|
||||
pending_probes := pending_probes & ~UIntToOH(curr_p_id)
|
||||
}
|
||||
|
||||
// Handle releases, which may have data to be written back
|
||||
val matches = io.matches.irel
|
||||
io.inner.release.ready := (!io.irel().hasData() || io.outer.acquire.ready) && matches
|
||||
when(io.inner.release.valid && matches) {
|
||||
when(io.irel().hasData()) {
|
||||
io.outer.acquire.valid := Bool(true)
|
||||
when(io.outer.acquire.ready) {
|
||||
when(oacq_data_done) {
|
||||
pending_ognt_ack := Bool(true)
|
||||
release_count := release_count - UInt(1)
|
||||
when(release_count === UInt(1)) {
|
||||
state := Mux(pending_outer_write, s_mem_write,
|
||||
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
||||
}
|
||||
}
|
||||
}
|
||||
} .otherwise {
|
||||
release_count := release_count - UInt(1)
|
||||
when(release_count === UInt(1)) {
|
||||
state := Mux(pending_outer_write, s_mem_write,
|
||||
Mux(pending_outer_read, s_mem_read, s_make_grant))
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
is(s_mem_write) { // Write data to outer memory
|
||||
io.outer.acquire.valid := !pending_ognt_ack && (!collect_iacq_data || iacq_data_valid(oacq_data_cnt))
|
||||
when(oacq_data_done) {
|
||||
pending_ognt_ack := Bool(true)
|
||||
state := Mux(pending_outer_read, s_mem_read, s_mem_resp)
|
||||
}
|
||||
}
|
||||
is(s_mem_read) { // Read data from outer memory (possibly what was just written)
|
||||
io.outer.acquire.valid := !pending_ognt_ack
|
||||
when(io.outer.acquire.fire()) { state := s_mem_resp }
|
||||
}
|
||||
is(s_mem_resp) { // Wait to forward grants from outer memory
|
||||
io.outer.grant.ready := io.inner.grant.ready
|
||||
io.inner.grant.valid := io.outer.grant.valid
|
||||
when(ignt_data_done) {
|
||||
state := Mux(io.ignt().requiresAck(), s_ack, s_idle)
|
||||
}
|
||||
}
|
||||
is(s_make_grant) { // Manufacture a local grant (some kind of permission upgrade)
|
||||
io.inner.grant.valid := Bool(true)
|
||||
when(io.inner.grant.ready) {
|
||||
state := Mux(io.ignt().requiresAck(), s_ack, s_idle)
|
||||
}
|
||||
}
|
||||
is(s_ack) { // Wait for transaction to complete
|
||||
io.inner.finish.ready := Bool(true)
|
||||
when(io.inner.finish.valid) { state := s_idle }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user