riscv/rocket-chip
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Don't speculatively refill I$ in uncacheable regions

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This commit is contained in:
Andrew Waterman
2016-07-09 01:08:52 -07:00
parent f7b392306e
commit 1699622730
5 changed files with 27 additions and 10 deletions
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2
rocket/src/main/scala/tlb.scala
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@ -32,6 +32,7 @@ class TLBResp(implicit p: Parameters) extends CoreBundle()(p) {
val xcpt_ld = Bool(OUTPUT)
val xcpt_st = Bool(OUTPUT)
val xcpt_if = Bool(OUTPUT)
val cacheable = Bool(OUTPUT)
}
class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
@ -111,6 +112,7 @@ class TLB(implicit val p: Parameters) extends Module with HasTLBParameters {
io.resp.xcpt_ld := bad_va || (!tlb_miss && !addr_prot.r) || (tlb_hit && !(r_array & hits).orR)
io.resp.xcpt_st := bad_va || (!tlb_miss && !addr_prot.w) || (tlb_hit && !(w_array & hits).orR)
io.resp.xcpt_if := bad_va || (!tlb_miss && !addr_prot.x) || (tlb_hit && !(x_array & hits).orR)
io.resp.cacheable := addrMap.isCacheable(paddr)
io.resp.miss := tlb_miss
io.resp.ppn := Mux(vm_enabled, Mux1H(hitsVec, ppns), io.req.bits.vpn(ppnBits-1,0))