riscv/rocket-chip
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loop host.in to host.out during reset

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This commit is contained in:
Andrew Waterman 2012-03-25 21:45:10 -07:00
parent f62a02ab54
commit 1666d3fbd7
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/slowio.scala
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@ -28,7 +28,7 @@ class slowIO[T <: Data](divisor: Int, hold_cycles: Int)(data: => T) extends Comp
val out_slow_bits = Reg() { data } val out_slow_bits = Reg() { data }
val fromhost_q = new queue(1)(data) val fromhost_q = new queue(1)(data)
fromhost_q.io.enq.valid := in_en && io.in_slow.valid && in_slow_rdy fromhost_q.io.enq.valid := in_en && (io.in_slow.valid && in_slow_rdy || reset)
fromhost_q.io.enq.bits := io.in_slow.bits fromhost_q.io.enq.bits := io.in_slow.bits
fromhost_q.io.deq <> io.in_fast fromhost_q.io.deq <> io.in_fast
@ -39,7 +39,7 @@ class slowIO[T <: Data](divisor: Int, hold_cycles: Int)(data: => T) extends Comp
when (out_en) { when (out_en) {
in_slow_rdy := fromhost_q.io.enq.ready in_slow_rdy := fromhost_q.io.enq.ready
out_slow_val := tohost_q.io.deq.valid out_slow_val := tohost_q.io.deq.valid
out_slow_bits := tohost_q.io.deq.bits out_slow_bits := Mux(reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits)
} }
io.in_slow.ready := in_slow_rdy io.in_slow.ready := in_slow_rdy