diff --git a/rocket b/rocket index 6624ac9d..3ed2fb60 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 6624ac9d3fb477649d95080b44e9e4656a56cb0a +Subproject commit 3ed2fb60ac05ddd25434b38bcb1ec7468ee94e4d diff --git a/src/main/scala/PublicConfigs.scala b/src/main/scala/PublicConfigs.scala index 3a560f62..1489330a 100644 --- a/src/main/scala/PublicConfigs.scala +++ b/src/main/scala/PublicConfigs.scala @@ -10,6 +10,8 @@ import rocket.Util._ class DefaultConfig extends ChiselConfig { val topDefinitions:World.TopDefs = { (pname,site,here) => pname match { + //RocketChip Parameters + case BuildTile => (r:Bool) => {new RocketTile(resetSignal = r)} //HTIF Parameters case HTIFWidth => Dump("HTIF_WIDTH", 16) case HTIFNSCR => 64 diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index d3d74197..6bfa51be 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -16,6 +16,7 @@ case object BuildDRAMSideLLC extends Field[(Int) => DRAMSideLLCLike] case object BuildCoherenceMaster extends Field[(Int) => CoherenceAgent] case object UseBackupMemoryPort extends Field[Boolean] case object Coherence extends Field[CoherencePolicyWithUncached] +case object BuildTile extends Field[(Bool)=>Tile] abstract trait TopLevelParameters extends UsesParameters { val htifW = params(HTIFWidth) @@ -24,6 +25,7 @@ abstract trait TopLevelParameters extends UsesParameters { val lsb = params(BankIdLSB) val refillCycles = params(MIFDataBeats) } + class OuterMemorySystem extends Module with TopLevelParameters { val io = new Bundle { val tiles = Vec.fill(params(NTiles)){new TileLinkIO}.flip @@ -132,7 +134,7 @@ class Top extends Module with TopLevelParameters { val io = new TopIO val resetSigs = Vec.fill(nTiles){Bool()} - val tileList = (0 until nTiles).map(r => Module(new Tile(resetSignal = resetSigs(r)))) + val tileList = (0 until nTiles).map(r => Module(params(BuildTile)(resetSigs(r)))) val uncore = Module(new Uncore) for (i <- 0 until nTiles) {